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    Low power multiplier
    1.
    发明授权
    Low power multiplier 失效
    低功率乘法器

    公开(公告)号：US5818743A

    公开(公告)日：1998-10-06

    申请号：US426349

    申请日：1995-04-21

    申请人： Wai Lee ,  Toshiyuki Sakuta

    发明人： Wai Lee ,  Toshiyuki Sakuta

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5338 ,  G06F2207/3884

    摘要： A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23 representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits 40 are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition. Finally, a plurality of delay elements 70 are placed in selected second signal lines so as to delay the arrival of the second signals to the at least some of the adder circuits so as to synchronize the arrival of the inputs to the at least some of the adder circuits.

    摘要翻译： 数字乘法器110，用于乘以表示被乘数的多个被乘数信号X0-X23和表示乘法器的多个乘法器信号Y0-Y23。 在其中，从乘法器信号和乘法器信号产生多个中间结果信号，例如部分乘积信号。 还提供了多个加法器电路40，用于将中间结果信号相加以产生表示乘法和乘法器相乘的结果的多个最终结果信号，其中至少一些加法器电路接收表示中间加法结果的第一信号， 至少两个先前的加法器级并且还接收表示作为仅一次加法的结果产生的中间结果的第二信号。 最后，将多个延迟元件70放置在所选择的第二信号线中，以便将第二信号的到达延迟到至少一些加法器电路，以便将输入的到达同步到至少一些 加法器电路。

    Low power multiplier
    2.
    发明授权
    Low power multiplier 失效
    低功率乘法器

    公开(公告)号：US06721774B1

    公开(公告)日：2004-04-13

    申请号：US09074197

    申请日：1998-05-07

    申请人： Wai Lee ,  Toshiyuki Sakuta

    发明人： Wai Lee ,  Toshiyuki Sakuta

    IPC分类号： G06F752

    CPC分类号： G06F7/5338 ,  G06F2207/3884

    摘要： A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23 representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits 40 are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition. Finally, a plurality of delay elements 70 are placed in selected second signal lines so as to delay the arrival of the second signals to the at least some of the adder circuits so as to synchronize the arrival of the inputs to the at least some of the adder circuits.

    摘要翻译： 数字乘法器110，用于乘以表示被乘数的多个被乘数信号X0-X23和表示乘法器的多个乘法器信号Y0-Y23。 在其中，从乘法器信号和乘法器信号产生多个中间结果信号，例如部分乘积信号。 还提供了多个加法器电路40，用于将中间结果信号相加以产生表示乘法和乘法器相乘的结果的多个最终结果信号，其中至少一些加法器电路接收表示中间加法结果的第一信号， 至少两个先前的加法器级并且还接收表示作为仅一次加法的结果产生的中间结果的第二信号。 最后，将多个延迟元件70放置在所选择的第二信号线中，以便将第二信号的到达延迟到至少一些加法器电路，以便将输入的到达同步到至少一些 加法器电路。

    Cleaning solutions including nucleophilic amine compound having reduction and oxidation potentials
    3.
    发明申请
    Cleaning solutions including nucleophilic amine compound having reduction and oxidation potentials 失效
    包括具有还原和氧化电位的亲核胺化合物的清洁溶液

    公开(公告)号：US20070078074A1

    公开(公告)日：2007-04-05

    申请号：US11633459

    申请日：2006-12-05

    申请人： Wai Lee ,  Charles Pittman ,  Robert Small

    发明人： Wai Lee ,  Charles Pittman ,  Robert Small

    IPC分类号： C11D7/32

    CPC分类号： G03F7/425 ,  C11D7/261 ,  C11D7/3218 ,  C11D7/3227 ,  C11D7/3245 ,  C11D7/3263 ,  C11D7/34 ,  C11D7/5009 ,  C11D7/5013 ,  C11D7/5022 ,  C11D11/0047 ,  C23G1/18

    摘要： A composition for removing resists and etching residue from substrates containing at least one nucleophilic amine compound having oxidation and reduction potentials, at least one organic solvent, water and, optionally, a chelating agent is described. The chelating agent is preferred to be included since it provides added stability and activity to the cleaning composition so that the composition has long term effectiveness. If a chelating agent is not present, the composition, while providing for adequate stripping and cleaning upon initial use of the composition following mixing, has only short term stability. In this latter instance, the nucleophilic amine compound and organic solvent components of the composition preferably are maintained separate from each other until it is desired to use the composition. Thereafter, the components are combined. Following use of the composition, the non-used portion of the composition can be disposed of or be reactivated by the addition of a chelating agent.

    摘要翻译： 描述了用于去除抗蚀剂并从含有至少一种具有氧化和还原电位的亲核胺化合物的底物蚀刻残余物的组合物，至少一种有机溶剂，水和任选的螯合剂。 优选包含螯合剂，因为它为清洁组合物提供了增加的稳定性和活性，使得组合物具有长期有效性。 如果不存在螯合剂，组合物在混合后初始使用组合物时提供足够的剥离和清洁，仅具有短期的稳定性。 在后一种情况下，组合物的亲核胺化合物和有机溶剂组分优选彼此保持分开，直到期望使用该组合物。 此后，组合组件。 使用组合物后，组合物的未使用部分可以通过加入螯合剂来处理或再活化。

    PWM DIGITAL AMPLIFIER WITH HIGH-ORDER LOOP FILTER
    4.
    发明申请
    PWM DIGITAL AMPLIFIER WITH HIGH-ORDER LOOP FILTER 有权
    PWM数字放大器与高阶环路滤波器

    公开(公告)号：US20060158247A1

    公开(公告)日：2006-07-20

    申请号：US11308123

    申请日：2006-03-07

    申请人： Wai Lee

    发明人： Wai Lee

    IPC分类号： H03F3/38

    CPC分类号： H03F3/217 ,  H03F1/26 ,  H03F1/32 ,  H03F2200/264 ,  H03F2200/351 ,  H03F2200/372

    摘要： An improved PWM amplifier is disclosed that uses multiple integrators in the loop filter to provide high loop gain across the frequency band-of-interest. The frequency characteristics of the loop filter are optimized to distribute large loop gains across the entire band to provide large suppression of noise and distortions generated in the modulation and output stages.

    摘要翻译： 公开了一种改进的PWM放大器，其使用环路滤波器中的多个积分器来提供跨越频带的高环路增益。 环路滤波器的频率特性被优化以在整个频带上分配大的环路增益，以提供在调制和输出级中产生的噪声和失真的大的抑制。

    Method and device for displaying animated navigation information
    5.
    发明授权
    Method and device for displaying animated navigation information 有权
    用于显示动画导航信息的方法和装置

    公开(公告)号：US06434484B1

    公开(公告)日：2002-08-13

    申请号：US09942297

    申请日：2001-08-29

    申请人： Wai Lee

    发明人： Wai Lee

    IPC分类号： G01C2126

    CPC分类号： G01S19/13 ,  G01C21/20

    摘要： A method and device for displaying animated navigation information has a processor, a memory, a display, and an input, housed in a portable, handheld housing. In various embodiments of the present invention, a plurality of frames are stored in memory, wherein each frame includes data indicative of a still-shot of a portion of an animated sequence represented by the total plurality of frames. The processor retrieves the frames in sequence for display on the display, such that successively displaying each of the frames on the display presents a visualization on the display of animated movement. In one aspect of the invention, animation is provided upon power up of the unit to provide the user with an indication of the nature of use and features of the unit. In another aspect of the invention, animation is provided to provide an indication to the user of satellite signal acquisition for use in navigation purposes. In another aspect of the invention, a graphical menu driven system is provided, such that upon entry of menu selection, a graphical representation indicative of the selection made appears on the display screen. In accordance with another aspect, as the user of the navigation unit moves with the navigation unit on his or her person, the navigation unit tracks the movement and provides an animated, graphical representation indicative of movement of the user.

    摘要翻译： 用于显示动画导航信息的方法和装置具有容纳在便携式手持外壳中的处理器，存储器，显示器和输入。 在本发明的各种实施例中，多个帧被存储在存储器中，其中每个帧包括指示由多个帧的总数表示的动画序列的一部分的静止图像的数据。 处理器依次检索帧以在显示器上显示，使得连续显示显示器上的每个帧在动画移动的显示上呈现可视化。 在本发明的一个方面，在单元上电时提供动画，以向用户提供该单元的使用性质和特征的指示。 在本发明的另一方面，提供动画以向用户提供用于导航目的的卫星信号采集的指示。 在本发明的另一方面，提供了一种图形菜单驱动系统，使得在进入菜单选择时，在显示屏上出现指示进行选择的图形表示。 根据另一方面，当导航单元的用户随着导航单元在他或她的人身上移动时，导航单元跟踪移动并提供表示用户移动的动画图形表示。

    Variable exposure photolithography
    8.
    发明申请
    Variable exposure photolithography 审中-公开
    可变曝光光刻

    公开(公告)号：US20070082432A1

    公开(公告)日：2007-04-12

    申请号：US11515798

    申请日：2006-09-06

    申请人： Wai Lee

    发明人： Wai Lee

    IPC分类号： H01L21/84 ,  H01L21/00

    CPC分类号： H01L27/1288 ,  H01L27/1214

    摘要： A method of forming a thin film transistor on a substrate including an insulating layer and layers of etchable material over the insulating layer by depositing a layer of photoresist made of polymers that are altered by actinic energy. In the method, an amine cross-linking agent is used with portions of the photoresist. The photoresist is differentially exposed to actinic energy to convert portions of the photoresist and portions are removed. Etching is selectively performed, followed by development of the remaining photoresist, followed by additional etching.

    摘要翻译： 通过沉积由光化能改变的聚合物制成的光致抗蚀剂层，在绝缘层上形成薄膜晶体管的方法，该方法包括绝缘层和可蚀刻材料层。 在该方法中，胺交联剂与光致抗蚀剂的一部分一起使用。 光致抗蚀剂差别地暴露于光化能以转换部分光致抗蚀剂并且部分被去除。 选择性地进行蚀刻，随后开发剩余的光致抗蚀剂，然后进行另外的蚀刻。

    Delta-sigma analog-to-digital converter suitable for use in a radio receiver channel
    9.
    发明申请
    Delta-sigma analog-to-digital converter suitable for use in a radio receiver channel 失效
    适用于无线电接收机通道的Delta-sigma模数转换器

    公开(公告)号：US20070080843A1

    公开(公告)日：2007-04-12

    申请号：US11249236

    申请日：2005-10-12

    申请人： Wai Lee ,  Xudong Zhao ,  Amit Kumar ,  Jianping Wen ,  Garry Link

    发明人： Wai Lee ,  Xudong Zhao ,  Amit Kumar ,  Jianping Wen ,  Garry Link

    IPC分类号： H03M1/12

    CPC分类号： H03M3/452 ,  H03H11/04 ,  H03H17/0664 ,  H03H2218/04 ,  H03H2218/10 ,  H03M3/424 ,  H03M3/448 ,  H03M3/454 ,  H03M3/462

    摘要： A radio receiver channel includes an analog front end and a digital signal processing section coupled together by an analog-to-digital converter (ADC) having a delta-sigma modulator coupled to a first digital decimation filter, which is coupled to second digital decimation filter, wherein the first decimation filter includes a source of finite impulse response coefficients coupled so as to provide a plurality of coefficients. The delta-sigma modulator includes a loop filter having a plurality of serially coupled integrators, and a multi-bit quantizer coupled to the loop filter; the multi-bit quantizer including an ADC operable to produce a multi-bit digital output signal, the ADC coupled to a DAC having dual DAC feedback loops, and a dynamic element matching function. In one embodiment, the delta-sigma modulator includes a fifth-order loop filter having five serially coupled integrators with a feedback path from the output to the input of the fifth integrator and a feedback path from the output to the input of the third integrator.

    摘要翻译： 无线电接收机通道包括模拟前端和数字信号处理部分，该数字信号处理部分由具有耦合到第一数字抽取滤波器的Δ-Σ调制器的模数转换器（ADC）耦合在一起，该Δ-Σ调制器耦合到第二数字抽取滤波器 ，其中所述第一抽取滤波器包括耦合以便提供多个系数的有限脉冲响应系数的源。 Δ-Σ调制器包括具有多个串联耦合的积分器的环路滤波器和耦合到环路滤波器的多位量化器; 多位量化器包括可操作以产生多位数字输出信号的ADC，耦合到具有双DAC反馈回路的DAC的ADC和动态元件匹配功能。 在一个实施例中，Δ-Σ调制器包括具有五个串联耦合积分器的五阶环路滤波器，其具有从第五积分器的输出到输入的反馈路径以及从第三积分器的输出到输入的反馈路径。