利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.023 秒)

    Supply voltage generator for a display timing controller with current reuse
    1.
    发明授权
    Supply voltage generator for a display timing controller with current reuse 有权
    用于具有当前重用的显示定时控制器的电源电压发生器

    公开(公告)号：US08935551B2

    公开(公告)日：2015-01-13

    申请号：US13475043

    申请日：2012-05-18

    申请人： Wang Yu ,  Jae-Youl Lee ,  Jae-Jin Park

    发明人： Wang Yu ,  Jae-Youl Lee ,  Jae-Jin Park

    IPC分类号： G06F1/32 ,  G09G5/00 ,  H03K19/00 ,  G09G3/36 ,  G06F1/26 ,  G09G3/38

    CPC分类号： H03K19/0013 ,  G06F1/26 ,  G09G3/3611 ,  G09G3/38

    摘要： A semiconductor IC including a supply voltage generator, one or more first circuit blocks, and one or more second circuit blocks. The supply voltage generator is configured to generate a first supply voltage and a second supply voltage based on an external supply voltage, and to provide the first supply voltage to a first power bus and the second supply voltage to a second power bus. The first circuit blocks are connected between the first power bus and the second power bus, and the second circuit blocks are connected between the second power bus and ground.

    摘要翻译： 一种包括电源电压发生器，一个或多个第一电路块和一个或多个第二电路块的半导体IC。 电源电压发生器被配置为基于外部电源电压产生第一电源电压和第二电源电压，并且将第一电源电压提供给第一电源总线，并将第二电源电压提供给第二电力总线。 第一电路块连接在第一电源总线和第二电源总线之间，第二电路块连接在第二电源总线和地之间。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF SUPPLYING POWER TO THE SAME
    2.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF SUPPLYING POWER TO THE SAME 有权
    半导体集成电路及其供电方法

    公开(公告)号：US20120319765A1

    公开(公告)日：2012-12-20

    申请号：US13475043

    申请日：2012-05-18

    申请人： Wang Yu ,  Jae-Youl Lee ,  Jae-Jin Park

    发明人： Wang Yu ,  Jae-Youl Lee ,  Jae-Jin Park

    IPC分类号： G05F3/02

    CPC分类号： H03K19/0013 ,  G06F1/26 ,  G09G3/3611 ,  G09G3/38

    摘要： A semiconductor IC including a supply voltage generator, one or more first circuit blocks, and one or more second circuit blocks. The supply voltage generator is configured to generate a first supply voltage and a second supply voltage based on an external supply voltage, and to provide the first supply voltage to a first power bus and the second supply voltage to a second power bus. The first circuit blocks are connected between the first power bus and the second power bus, and the second circuit blocks are connected between the second power bus and ground.

    摘要翻译： 一种包括电源电压发生器，一个或多个第一电路块和一个或多个第二电路块的半导体IC。 电源电压发生器被配置为基于外部电源电压产生第一电源电压和第二电源电压，并且将第一电源电压提供给第一电源总线，并将第二电源电压提供给第二电力总线。 第一电路块连接在第一电源总线和第二电源总线之间，第二电路块连接在第二电源总线和地之间。

    Method of interfacing a high speed signal
    3.
    发明授权
    Method of interfacing a high speed signal 有权
    连接高速信号的方法

    公开(公告)号：US07593468B2

    公开(公告)日：2009-09-22

    申请号：US11047255

    申请日：2005-01-31

    申请人： Jae-Jin Park ,  Seung-Bin You

    发明人： Jae-Jin Park ,  Seung-Bin You

    IPC分类号： H04B14/04

    CPC分类号： H04L25/4919

    摘要： In a method of interfacing a high-speed signal, a series of digital signals are received from a transmitter in response to a clock signal. The received digital signal is coded based on a K-L level pulse amplitude modulation system in response to the clock signal, wherein K and L are natural numbers and K≠L. The received digital signal is repeatedly coded and the coded digital signal is transferred to a receiver. As a result, crosstalk between adjacent channels may be reduced.

    摘要翻译： 在接收高速信号的方法中，响应于时钟信号从发射机接收一系列数字信号。 所接收的数字信号根据时钟信号基于K-L电平脉冲幅度调制系统进行编码，其中K和L是自然数，K

    System-on-chip including body bias voltage generator
    4.
    发明授权
    System-on-chip including body bias voltage generator 有权
    系统级芯片包括体偏置电压发生器

    公开(公告)号：US09467135B2

    公开(公告)日：2016-10-11

    申请号：US14717379

    申请日：2015-05-20

    申请人： Sang-Kyu Kim ,  Jae-Jin Park ,  Seung-Hoon Lee

    发明人： Sang-Kyu Kim ,  Jae-Jin Park ,  Seung-Hoon Lee

    IPC分类号： H03K17/00 ,  H03K17/041 ,  H03K17/14 ,  H03K17/16

    CPC分类号： H03K17/04106 ,  H03K17/145 ,  H03K17/162 ,  H03K2217/0018

    摘要： A system-on-chip includes a body bias voltage generator having a voltage divider and a filter. The voltage divider includes a switched capacitor circuit and a resistor circuit. The switched capacitor circuit operates based on a first clock signal and a second clock signal. The resistor circuit outputs a first voltage through a first node, which is coupled to the switched capacitor circuit and the resistor circuit. The first and second clock signals have a same frequency. The filter performs a filtering operation on the first voltage to generate a body bias voltage.

    摘要翻译： 芯片上系统包括具有分压器和滤波器的体偏置电压发生器。 分压器包括开关电容电路和电阻电路。 开关电容器电路基于第一时钟信号和第二时钟信号进行工作。 电阻电路通过第一节点输出第一电压，该第一节点耦合到开关电容器电路和电阻电路。 第一和第二时钟信号具有相同的频率。 滤波器对第一电压进行滤波操作以产生体偏置电压。

    Temperature controlled oscillator and temperature sensor including the same
    5.
    发明授权
    Temperature controlled oscillator and temperature sensor including the same 有权
    温度控制振荡器和温度传感器包括相同的

    公开(公告)号：US09191015B2

    公开(公告)日：2015-11-17

    申请号：US14159492

    申请日：2014-01-21

    申请人： Sung-Jin Kim ,  Jae-Jin Park

    发明人： Sung-Jin Kim ,  Jae-Jin Park

    IPC分类号： H03K3/0231 ,  H03L7/00 ,  H03L1/02 ,  H03B5/24

    CPC分类号： H03L7/00 ,  H03B5/24 ,  H03L1/022

    摘要： A temperature controlled oscillator includes an oscillation unit and a filter unit. The oscillation unit is configured to generate at least one reference voltage based on a supply voltage and a ground voltage, and to generate an oscillation signal having a period varying according to a temperature, the oscillation unit configured to generate the oscillation signal based on a filter voltage and the at least one reference voltage. The filter unit is configured to generate the filter voltage based on the oscillation signal.

    摘要翻译： 温度控制振荡器包括振荡单元和滤波器单元。 振荡单元被配置为基于电源电压和接地电压产生至少一个参考电压，并且产生具有根据温度变化的周期的振荡信号，所述振荡单元被配置为基于滤波器产生振荡信号 电压和至少一个参考电压。 滤波器单元被配置为基于振荡信号产生滤波电压。

    Display device transferring data signal with clock
    6.
    发明授权
    Display device transferring data signal with clock 有权
    显示设备用时钟传输数据信号

    公开(公告)号：US08314763B2

    公开(公告)日：2012-11-20

    申请号：US12167393

    申请日：2008-07-03

    申请人： Jae-Jin Park ,  Dong-Uk Park ,  Jin-Ho Seo

    发明人： Jae-Jin Park ,  Dong-Uk Park ,  Jin-Ho Seo

    IPC分类号： G09G3/36

    CPC分类号： G09G3/2096 ,  G09G3/3685 ,  G09G5/008 ,  G09G2330/06

    摘要： A display device includes; a panel, a timing controller generating an embedded clock data signal combining image data and a clock signal, and a column driver driving the panel in response to the embedded clock data signal. The data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, and the timing controller determines one of the three voltage levels for a current data bit (DIN[n]) within the embedded clock data signal in relation to a voltage level of a previous data bit (DIN[n−1]) within the embedded clock data signal.

    摘要翻译： 显示装置包括： 面板，产生组合图像数据和时钟信号的嵌入式时钟数据信号的定时控制器和响应于嵌入的时钟数据信号驱动面板的列驱动器。 嵌入式时钟数据信号中的数据位以三电平信令方案中的三个电压电平中的一个通信，并且定时控制器确定嵌入式时钟数据信号中当前数据位（DIN [n]）的三个电压电平之一 时钟数据信号相对于嵌入式时钟数据信号中的先前数据位（DIN [n-1]）的电压电平。

    DIGITAL PHASE FREQUENCY DETECTOR, DIGITAL PHASE LOCKED LOOP INCLUDING THE SAME AND METHOD OF DETECTING PHASE AND FREQUENCY OF OUTPUT SIGNAL
    7.
    发明申请
    DIGITAL PHASE FREQUENCY DETECTOR, DIGITAL PHASE LOCKED LOOP INCLUDING THE SAME AND METHOD OF DETECTING PHASE AND FREQUENCY OF OUTPUT SIGNAL 有权
    数字相位频率检测器，数字相位锁定环路及其相位检测和输出信号频率检测方法

    公开(公告)号：US20120183104A1

    公开(公告)日：2012-07-19

    申请号：US13315476

    申请日：2011-12-09

    申请人： JONG-PHIL HONG ,  Ji-Hyun Kim ,  Jae-Jin Park

    发明人： JONG-PHIL HONG ,  Ji-Hyun Kim ,  Jae-Jin Park

    IPC分类号： H04L27/06

    CPC分类号： H03L7/113 ,  H03L7/085 ,  H03L7/1077

    摘要： A digital phase frequency detector includes a detection unit, a reset unit and a phase comparison unit. The detection unit detects edges of a reference signal and a feedback input signal to generate a reference edge signal and a feedback edge signal. The reset unit generates a reset signal resetting the detection unit based upon the reference edge signal and the feedback edge signal. The phase comparison unit generates first and second phase comparison signals based upon the reference edge signal and the feedback edge signal. The phase comparison unit includes a first flip-flop generating a first comparison signal based upon the reference edge signal and the feedback edge signal, a second flip-flop generating a second comparison signal based upon the reference edge signal and the feedback edge signal, and a latch block latching the first and second comparison signals to generate the first and second phase comparison signals.

    摘要翻译： 数字相位频率检测器包括检测单元，复位单元和相位比较单元。 检测单元检测参考信号和反馈输入信号的边沿以产生参考边缘信号和反馈边缘信号。 复位单元基于参考边沿信号和反馈边沿信号产生复位检测单元的复位信号。 相位比较单元基于参考边缘信号和反馈边缘信号产生第一和第二相位比较信号。 相位比较单元包括基于参考边缘信号和反馈边缘信号产生第一比较信号的第一触发器，基于参考边缘信号和反馈边缘信号产生第二比较信号的第二触发器，以及 锁存块锁存第一和第二比较信号以产生第一和第二相位比较信号。

    Phase locked loop without a charge pump and integrated circuit having the same
    9.
    发明授权
    Phase locked loop without a charge pump and integrated circuit having the same 失效
    没有电荷泵的锁相环和具有相同功能的集成电路

    公开(公告)号：US07636000B2

    公开(公告)日：2009-12-22

    申请号：US11975158

    申请日：2007-10-18

    申请人： Jae-Jin Park

    发明人： Jae-Jin Park

    IPC分类号： H03L7/06

    CPC分类号： H03L7/093 ,  H03L7/0896 ,  H03L7/183

    摘要： A phase locked loop includes a phase-frequency detector and a loop filter. The phase-frequency detector compares phases of an input signal and a feedback signal to generate first and second control signals. The loop filter includes a pull-up resistor, a pull-down resistor and a capacitance unit. The loop filter receives a first reference voltage to charge the capacitance unit through a path formed by the pull-up resistor to the capacitance unit, receives a second reference voltage to discharge the capacitance unit through a path formed by the pull-down resistor to the capacitance unit and outputs a control voltage generated based on a charge amount of the charged capacitance unit. Therefore, the phase locked loop can operate at a relatively low voltage and can operate based on a control voltage with a wide input range.

    摘要翻译： 锁相环包括相位频率检测器和环路滤波器。 相位频率检测器对输入信号和反馈信号的相位进行比较，以产生第一和第二控制信号。 环路滤波器包括一个上拉电阻，一个下拉电阻和一个电容单元。 环路滤波器接收第一参考电压，以通过由上拉电阻器形成的路径向电容单元充电电容单元，接收第二参考电压，以通过由下拉电阻器形成的路径将电容单元放电到 电容单元，并输出基于充电电容单元的充电量产生的控制电压。 因此，锁相环可以在相对低的电压下工作，并且可以基于宽输入范围的控制电压进行工作。

    Low voltage data transmitting circuit and associated methods
    10.
    发明申请
    Low voltage data transmitting circuit and associated methods 审中-公开
    低压数据传输电路及相关方法

    公开(公告)号：US20080218292A1

    公开(公告)日：2008-09-11

    申请号：US12073313

    申请日：2008-03-04

    申请人： Dong-Uk Park ,  Jin-Ho Seo ,  Jae-Jin Park

    发明人： Dong-Uk Park ,  Jin-Ho Seo ,  Jae-Jin Park

    IPC分类号： H01P5/12

    CPC分类号： G06F13/4086

    摘要： A low voltage data transmitting circuit (LVDTC) may be connected to a first transmission line that transmits a first voltage signal to a receiver and a second transmission line that transmits a second voltage signal to the receiver. The LVDTC includes a first resistor coupled to the first transmission line, a second resistor coupled to the second transmission line, and a control unit coupled to the first transmission line and the second transmission line, the control unit being configured to control voltage levels of the first and second voltage signals such that the voltage levels of the first and second voltage signals are higher than a ground voltage level of the receiver, wherein the first and second voltage signals may constitute a differential pair.

    摘要翻译： 低压数据发送电路（LVDTC）可以连接到向接收机发送第一电压信号的第一传输线和向接收机发送第二电压信号的第二传输线。 LVDTC包括耦合到第一传输线的第一电阻器，耦合到第二传输线的第二电阻器和耦合到第一传输线路和第二传输线路的控制单元，该控制单元被配置为控制 第一和第二电压信号，使得第一和第二电压信号的电压电平高于接收器的接地电压电平，其中第一和第二电压信号可以构成差分对。