公开(公告)号：US06605956B2

公开(公告)日：2003-08-12

申请号：US09797368

申请日：2001-03-01

申请人： Warren M Farnworth ,  James M. Wark ,  Eric S. Nelson ,  Kevin G. Duesman

发明人： Warren M Farnworth ,  James M. Wark ,  Eric S. Nelson ,  Kevin G. Duesman

IPC分类号： G01R3128

CPC分类号： G11C29/785 ,  G01R31/2884 ,  G01R31/31701 ,  G01R31/31719 ,  G01R31/318513 ,  G11C29/1201 ,  G11C29/46 ,  G11C29/80 ,  G11C29/808 ,  H01L22/22 ,  H01L2224/48091 ,  H01L2224/48227 ,  H04J2203/0062 ,  H01L2924/00014

摘要： An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging. A method for performing such testing once the test mode has been initiated and for repairing any failing elements found during testing includes providing test signals to the dice, receiving response signals from the dice, evaluating the response signals to identify any failing elements in the dice, programming the failing elements' addresses into anti-fuses in the dice with a programming voltage, confirming that the addresses are programmed by determining the resistance of the anti-fuses, re-testing the dice, receiving response signals from the retested dice, and evaluating the response signals to confirm all repairs.

摘要翻译： 诸如多芯片模块（MCM）的IC模块包括多个IC芯片，每个具有测试模式使能焊盘，例如输出使能焊盘。 集成到MCM基板中的保险丝将每个管芯的测试模式使能接合焊盘连接到MCM的无连接（N / C）引脚之一，并且连接到衬底中的电阻将测试模式使能焊盘连接到MCM的一个接地 针脚。 通过向测试模式施加电源电压，使焊盘通过N / C引脚，在骰子中启动测试模式。 一旦测试完成，保险丝可能会被熔断，并且施加到测试模式的接地电压使得接合焊盘通过接地引脚，使得电阻器禁用骰子中的测试模式并启动操作模式。 因此，封装在IC模块中的裸片可以在封装后进行测试。 一旦测试模式已经启动并且用于修复在测试期间发现的任何故障元件，执行这种测试的方法包括向骰子提供测试信号，从骰子接收响应信号，评估响应信号以识别骰子中的任何故障元件， 使用编程电压将故障元件的地址编程为骰子中的防熔丝，通过确定抗熔丝的电阻，重新测试骰子，接收重新测试的骰子的响应信号，并评估 响应信号确认所有维修。

公开(公告)号：US07063524B2

公开(公告)日：2006-06-20

申请号：US10224103

申请日：2002-08-20

申请人： Warren M Farnworth ,  Kevin G. Duesman

发明人： Warren M Farnworth ,  Kevin G. Duesman

IPC分类号： B29C35/08

CPC分类号： B23K26/0734 ,  B29C64/135 ,  B29C2035/0838 ,  B29K2995/0073 ,  B33Y10/00 ,  B33Y30/00 ,  H01S3/0835

摘要： A stereolithographic (STL) apparatus for forming structures such as semiconductor die packages is described which uses a laser beam focused to a generally annular “spot” having an annulus of enhanced laser power surrounding a central “hole” of reduced (or no) laser power. The structures are formed of a stack of light-polymerized photopolymer layers. Scanning of a beam having power concentrated in the annulus enables simultaneous production of a self-supporting structure having at least semisolid, smooth lateral outer polymer walls and an upper hardened polymer skin extending over liquid polymer still lying between the walls. The structure may be subjected to heat or broad source light of suitable wavelength after removal from the STL apparatus to accelerate complete polymerization of the structure to a solid state.

摘要翻译： 描述了用于形成诸如半导体管芯封装的结构的立体光刻（STL）装置，其使用聚焦到大体上环形的“点”的激光束，所述“点”具有包围减少（或不）激光功率的中心“孔”的增强激光功率的环 。 该结构由一叠光聚合光聚合物层形成。 具有集中在环形空间中的光束的扫描使得能够同时生产具有至少半固体，光滑的侧向外聚合物壁和延伸在仍位于壁之间的液体聚合物上的上固化的聚合物表皮的自支撑结构。 在从STL装置去除之后，该结构可以经受合适波长的热源或宽源光，以促进结构完全聚合成固态。

公开(公告)号：US6094058A

公开(公告)日：2000-07-25

申请号：US949383

申请日：1997-10-14

申请人： David R. Hembree ,  Warren M Farnworth ,  Alan G. Wood ,  Salman Akram

发明人： David R. Hembree ,  Warren M Farnworth ,  Alan G. Wood ,  Salman Akram

IPC分类号： G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC分类号： H01L23/49838 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/80 ,  H05K3/4007 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2863 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423

摘要： A temporary package for a semiconductor die is provided. The temporary package has an outline and external contact configuration that are the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. The package includes a base, an interconnect and a force applying mechanism. The package base includes external contacts formed in a dense array, such as a land grid array (LGA), a pin grid array (PGA), a bumped grid array (BGA) or a perimeter array. The package base can be formed of ceramic or plastic with internal conductive lines using a ceramic lamination process, a 3-D molding process or a Cerdip formation process.