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    Optical gratings, lithography tools including such optical gratings and methods for using same for alignment
    3.
    发明申请
    Optical gratings, lithography tools including such optical gratings and methods for using same for alignment 失效
    光栅，包括这种光栅的光刻工具和用于对准的方法

    公开(公告)号：US20080094629A1

    公开(公告)日：2008-04-24

    申请号：US11584461

    申请日：2006-10-20

    申请人： Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

    发明人： Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

    IPC分类号： G01B11/00

    CPC分类号： G03F9/7049 ,  G03F9/7003

    摘要： Lithography tools and substrates are aligned by generating geometric interference patterns using optical gratings associated with the lithography tools and substrates. In some embodiments, the relative position between a substrate and lithography tool is adjusted to cause at least one geometric shape to have a predetermined size or shape representing acceptable alignment. In additional embodiments, Moiré patterns that exhibit varying sensitivity are used to align substrates and lithography tools. Furthermore, lithography tools and substrates are aligned by causing radiation to interact with optical gratings positioned between the lithography tools and substrates. Lithography tools include an optical grating configured to generate a portion of an interference pattern that exhibits a sensitivity that increases as the relative position between the tools and a substrate moves towards a predetermined alignment position.

    摘要翻译： 通过使用与光刻工具和衬底相关的光栅产生几何干涉图案来对准平版印刷工具和衬底。 在一些实施例中，调整衬底和光刻工具之间的相对位置以使得至少一个几何形状具有表示可接受对准的预定尺寸或形状。 在另外的实施例中，使用呈现不同灵敏度的莫尔图案来对准衬底和光刻工具。 此外，光刻工具和衬底通过使辐射与位于光刻工具和衬底之间的光栅相互作用来对准。 平版印刷工具包括光栅，其被配置为产生表现出灵敏度的一部分干涉图案，该灵敏度随着工具和基板之间的相对位置朝向预定对准位置移动而增加。

    Optical gratings, lithography tools including such optical gratings and methods for using same for alignment
    4.
    发明授权
    Optical gratings, lithography tools including such optical gratings and methods for using same for alignment 失效
    光栅，包括这种光栅的光刻工具和用于对准的方法

    公开(公告)号：US07612882B2

    公开(公告)日：2009-11-03

    申请号：US11584461

    申请日：2006-10-20

    申请人： Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

    发明人： Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

    IPC分类号： G01B11/00 ,  G01B11/14

    CPC分类号： G03F9/7049 ,  G03F9/7003

    摘要： Lithography tools and substrates are aligned by generating geometric interference patterns using optical gratings associated with the lithography tools and substrates. In some embodiments, the relative position between a substrate and lithography tool is adjusted to cause at least one geometric shape to have a predetermined size or shape representing acceptable alignment. In additional embodiments, Moiré patterns that exhibit varying sensitivity are used to align substrates and lithography tools. Furthermore, lithography tools and substrates are aligned by causing radiation to interact with optical gratings positioned between the lithography tools and substrates. Lithography tools include an optical grating configured to generate a portion of an interference pattern that exhibits a sensitivity that increases as the relative position between the tools and a substrate moves towards a predetermined alignment position.

    摘要翻译： 通过使用与光刻工具和衬底相关的光栅产生几何干涉图案来对准平版印刷工具和衬底。 在一些实施例中，调整衬底和光刻工具之间的相对位置以使得至少一个几何形状具有表示可接受对准的预定尺寸或形状。 在另外的实施例中，使用呈现不同灵敏度的莫尔图案来对准衬底和光刻工具。 此外，光刻工具和衬底通过使辐射与位于光刻工具和衬底之间的光栅相互作用来对准。 平版印刷工具包括光栅，其被配置为产生表现出灵敏度的一部分干涉图案，该灵敏度随着工具和基板之间的相对位置朝向预定对准位置移动而增加。

    Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays
    5.
    发明授权
    Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays 失效
    基于隧道电阻器结的微米级/纳米级解复用器阵列

    公开(公告)号：US07319416B2

    公开(公告)日：2008-01-15

    申请号：US11343325

    申请日：2006-01-30

    申请人： Warren Robinett ,  Gregory S. Snider ,  Duncan Stewart ,  Joseph Straznicky

    发明人： Warren Robinett ,  Gregory S. Snider ,  Duncan Stewart ,  Joseph Straznicky

    IPC分类号： H03M7/14

    CPC分类号： G11C8/10 ,  G11C13/0023 ,  H03M13/51

    摘要： Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the present invention, an encoder-demultiplexer comprises a number of input signal lines and an encoder that generates an n-bit-constant-weight-code code-word internal address for each different input address received on the input signal lines. The encoder-demultiplexer includes n microscale signal lines on which an n-bit-constant-weight-code code-word internal address is output by the encoder, where each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address. The encoder-demultiplexer also includes a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with the n microscale signal lines via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal address.

    摘要翻译： 本发明的各种实施例涉及包括隧穿电阻器纳米线结的解复用器，以及纳米线寻址方法，用于在纳米尺度和混合尺度解复用器中可靠地寻址纳米线信号线。 在本发明的一个实施例中，编码器 - 解复用器包括多个输入信号线和一个编码器，其生成在输入信号线上接收的每个不同输入地址的n位恒权重码码字内部地址 。 编码器 - 解复用器包括n个微米级信号线，编码器输出n位恒定权重码码字内部地址，其中每个微信号线承载n位恒权重码内部地址的一位， 代码字内部地址。 编码器 - 解复用器还包括通过隧道电阻器结与n个微米级信号线互连的多个编码器 - 解复用器寻址的纳米线信号线，编码器 - 解复用器寻址的纳米线信号线每个与n比特恒权重信号线相关联， 代码字内部地址。

    IMPLEMENTING LOGIC CIRCUITS WITH MEMRISTORS
    6.
    发明申请
    IMPLEMENTING LOGIC CIRCUITS WITH MEMRISTORS 有权
    用电磁阀实现逻辑电路

    公开(公告)号：US20140028347A1

    公开(公告)日：2014-01-30

    申请号：US13561978

    申请日：2012-07-30

    申请人： Warren Robinett ,  R. Stanley Williams

    发明人： Warren Robinett ,  R. Stanley Williams

    IPC分类号： H03K19/173

    CPC分类号： H03K19/173 ,  G11C13/0007 ,  H03K19/17712 ,  H03K19/17728

    摘要： Implementing logic with memristors may include circuitry with at least three memristors and a bias resistor in a logic cell. One of the at least three memristors is an output memristor within the logic cell and the other memristors of the at least three memristors are input memristors. Each of the at least three memristors and the bias resistor are electrically connected to voltage sources wherein each voltage applied to each of the at least three memristors and the bias resistor and resistance states of the at least three memristors determine a resistance state of the output memristor.

    摘要翻译： 使用忆阻器实现逻辑可以包括在逻辑单元中具有至少三个忆阻器和偏置电阻器的电路。 至少三个忆阻器中的一个是逻辑单元内的输出忆阻器，至少三个忆阻器的其他忆阻器是输入忆阻器。 至少三个忆阻器和偏置电阻器中的每一个电连接到电压源，其中施加到至少三个忆阻器中的每一个的每个电压和至少三个忆阻器的偏置电阻器和电阻状态确定输出忆阻器的电阻状态 。

    Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding
    7.
    发明授权
    Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding 有权
    使用序列复制和错误控制编码的缺陷和容错解复用器

    公开(公告)号：US07872502B2

    公开(公告)日：2011-01-18

    申请号：US11484961

    申请日：2006-07-12

    申请人： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

    发明人： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

    IPC分类号： H03K19/094

    CPC分类号： H03K19/007 ,  G06F11/1076 ,  H03K19/00315

    摘要： One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.

    摘要翻译： 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。

    Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding
    8.
    发明申请
    Defect-and-failure-tolerant demultiplexer using series replication and error-control encoding 有权
    使用系列复制和错误控制编码的缺陷和容错解复用器

    公开(公告)号：US20080013393A1

    公开(公告)日：2008-01-17

    申请号：US11484961

    申请日：2006-07-12

    申请人： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

    发明人： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

    IPC分类号： G11C17/18

    CPC分类号： H03K19/007 ,  G06F11/1076 ,  H03K19/00315

    摘要： One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.

    摘要翻译： 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。

    Implementing logic circuits with memristors
    9.
    发明授权
    Implementing logic circuits with memristors 有权
    用忆阻器实现逻辑电路

    公开(公告)号：US08773167B2

    公开(公告)日：2014-07-08

    申请号：US13561978

    申请日：2012-07-30

    申请人： Warren Robinett ,  R. Stanley Williams

    发明人： Warren Robinett ,  R. Stanley Williams

    IPC分类号： H03K19/00 ,  G11C11/00

    CPC分类号： H03K19/173 ,  G11C13/0007 ,  H03K19/17712 ,  H03K19/17728

    摘要： Implementing logic with memristors may include circuitry with at least three memristors and a bias resistor in a logic cell. One of the at least three memristors is an output memristor within the logic cell and the other memristors of the at least three memristors are input memristors. Each of the at least three memristors and the bias resistor are electrically connected to voltage sources wherein each voltage applied to each of the at least three memristors and the bias resistor and resistance states of the at least three memristors determine a resistance state of the output memristor.

    摘要翻译： 使用忆阻器实现逻辑可以包括在逻辑单元中具有至少三个忆阻器和偏置电阻器的电路。 至少三个忆阻器中的一个是逻辑单元内的输出忆阻器，至少三个忆阻器的其他忆阻器是输入忆阻器。 至少三个忆阻器和偏置电阻器中的每一个电连接到电压源，其中施加到至少三个忆阻器中的每一个的每个电压和至少三个忆阻器的偏置电阻器和电阻状态确定输出忆阻器的电阻状态 。

    DEFECT-AND-FAILURE-TOLERANT DEMULTIPLEXER USING SERIES REPLICATION AND ERROR-CONTROL ENCODING
    10.
    发明申请
    DEFECT-AND-FAILURE-TOLERANT DEMULTIPLEXER USING SERIES REPLICATION AND ERROR-CONTROL ENCODING 审中-公开
    使用系列复制和错误控制编码的缺陷和失败的解复用器

    公开(公告)号：US20110057683A1

    公开(公告)日：2011-03-10

    申请号：US12947585

    申请日：2010-11-16

    申请人： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

    发明人： Warren Robinett ,  Philip J. Kuekes ,  R. Stanley Williams

    IPC分类号： H03K19/003

    CPC分类号： H03K19/007 ,  G06F11/1076 ,  H03K19/00315

    摘要： One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.

    摘要翻译： 本发明的一个实施例是一种用于构建缺陷和容错解复用器的方法。 该方法适用于纳米尺度，微米级或更大规模的解复用器电路。 解复用器电路可以被视为一组与门，每个与门包括多个地址线或地址线导出的信号线之间的可逆切换互连以及输出信号线。 每个可逆切换互连包括一个或多个可逆切换元件。 在某些解复用器实施例中，NMOS和/或PMOS晶体管被用作可逆切换元件。 在表示本发明的一个实施例的方法中，在每个可逆切换互连中使用两个或更多个串联连接的晶体管，使得比串联互连晶体管的数量少一个的短缺陷不会导致可逆地失效 可切换互连。 此外，误差控制编码技术用于引入附加的地址线导出的信号线和附加的可切换互连，使得即使当多个单独的可切换互连是开放缺陷时，解复用器也可以起作用。