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    Optical gratings, lithography tools including such optical gratings and methods for using same for alignment
    1.
    发明申请
    Optical gratings, lithography tools including such optical gratings and methods for using same for alignment 失效
    光栅，包括这种光栅的光刻工具和用于对准的方法

    公开(公告)号：US20080094629A1

    公开(公告)日：2008-04-24

    申请号：US11584461

    申请日：2006-10-20

    申请人： Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

    发明人： Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

    IPC分类号： G01B11/00

    CPC分类号： G03F9/7049 ,  G03F9/7003

    摘要： Lithography tools and substrates are aligned by generating geometric interference patterns using optical gratings associated with the lithography tools and substrates. In some embodiments, the relative position between a substrate and lithography tool is adjusted to cause at least one geometric shape to have a predetermined size or shape representing acceptable alignment. In additional embodiments, Moiré patterns that exhibit varying sensitivity are used to align substrates and lithography tools. Furthermore, lithography tools and substrates are aligned by causing radiation to interact with optical gratings positioned between the lithography tools and substrates. Lithography tools include an optical grating configured to generate a portion of an interference pattern that exhibits a sensitivity that increases as the relative position between the tools and a substrate moves towards a predetermined alignment position.

    摘要翻译： 通过使用与光刻工具和衬底相关的光栅产生几何干涉图案来对准平版印刷工具和衬底。 在一些实施例中，调整衬底和光刻工具之间的相对位置以使得至少一个几何形状具有表示可接受对准的预定尺寸或形状。 在另外的实施例中，使用呈现不同灵敏度的莫尔图案来对准衬底和光刻工具。 此外，光刻工具和衬底通过使辐射与位于光刻工具和衬底之间的光栅相互作用来对准。 平版印刷工具包括光栅，其被配置为产生表现出灵敏度的一部分干涉图案，该灵敏度随着工具和基板之间的相对位置朝向预定对准位置移动而增加。

    Optical gratings, lithography tools including such optical gratings and methods for using same for alignment
    2.
    发明授权
    Optical gratings, lithography tools including such optical gratings and methods for using same for alignment 失效
    光栅，包括这种光栅的光刻工具和用于对准的方法

    公开(公告)号：US07612882B2

    公开(公告)日：2009-11-03

    申请号：US11584461

    申请日：2006-10-20

    申请人： Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

    发明人： Wei Wu ,  Warren Robinett ,  Shih-Yuan Wang ,  Jun Gao ,  Zhaoning Yu

    IPC分类号： G01B11/00 ,  G01B11/14

    CPC分类号： G03F9/7049 ,  G03F9/7003

    摘要： Lithography tools and substrates are aligned by generating geometric interference patterns using optical gratings associated with the lithography tools and substrates. In some embodiments, the relative position between a substrate and lithography tool is adjusted to cause at least one geometric shape to have a predetermined size or shape representing acceptable alignment. In additional embodiments, Moiré patterns that exhibit varying sensitivity are used to align substrates and lithography tools. Furthermore, lithography tools and substrates are aligned by causing radiation to interact with optical gratings positioned between the lithography tools and substrates. Lithography tools include an optical grating configured to generate a portion of an interference pattern that exhibits a sensitivity that increases as the relative position between the tools and a substrate moves towards a predetermined alignment position.

    摘要翻译： 通过使用与光刻工具和衬底相关的光栅产生几何干涉图案来对准平版印刷工具和衬底。 在一些实施例中，调整衬底和光刻工具之间的相对位置以使得至少一个几何形状具有表示可接受对准的预定尺寸或形状。 在另外的实施例中，使用呈现不同灵敏度的莫尔图案来对准衬底和光刻工具。 此外，光刻工具和衬底通过使辐射与位于光刻工具和衬底之间的光栅相互作用来对准。 平版印刷工具包括光栅，其被配置为产生表现出灵敏度的一部分干涉图案，该灵敏度随着工具和基板之间的相对位置朝向预定对准位置移动而增加。

    Interconnection architectures for multilayer crossbar circuits
    5.
    发明授权
    Interconnection architectures for multilayer crossbar circuits 有权
    多层交叉电路的互连架构

    公开(公告)号：US08253443B2

    公开(公告)日：2012-08-28

    申请号：US12912647

    申请日：2010-10-26

    申请人： Warren Robinett

    发明人： Warren Robinett

    IPC分类号： H03K19/00 ,  H01L25/00 ,  H01L21/82 ,  H01L21/3205

    CPC分类号： H01L27/2481 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/146

    摘要： An interconnection architecture for multilayer circuits includes metal-insulator transition channels interposed between address leads and each bar in the multilayer circuit. An extrinsic variable transducer selectively transitions the metal-insulator channels between insulating and conducting states to selectively connect and disconnect the bars and the address leads. A method for accessing a programmable crosspoint device within a multilayer crossbar circuit is also provided.

    摘要翻译： 用于多层电路的互连架构包括插入在多层电路中的地址引线和每个条之间的金属 - 绝缘体转换通道。 外部可变传感器在绝缘和导通状态之间选择性地转移金属 - 绝缘体通道，以选择性地连接和断开条和地址引线。 还提供了一种用于访问多层交叉电路内的可编程交叉点设备的方法。

    Interconnection Architectures for Multilayer Crossbar Circuits
    6.
    发明申请
    Interconnection Architectures for Multilayer Crossbar Circuits 有权
    多层交叉电路互连架构

    公开(公告)号：US20120098566A1

    公开(公告)日：2012-04-26

    申请号：US12912647

    申请日：2010-10-26

    申请人： Warren Robinett

    发明人： Warren Robinett

    IPC分类号： H03K19/177 ,  H01L47/00

    CPC分类号： H01L27/2481 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/146

    摘要： An interconnection architecture for multilayer circuits includes metal-insulator transition channels interposed between address leads and each bar in the multilayer circuit. An extrinsic variable transducer selectively transitions the metal-insulator channels between insulating and conducting states to selectively connect and disconnect the bars and the address leads. A method for accessing a programmable crosspoint device within a multilayer crossbar circuit is also provided.

    摘要翻译： 用于多层电路的互连架构包括插入在多层电路中的地址引线和每个条之间的金属 - 绝缘体转换通道。 外部可变传感器在绝缘和导通状态之间选择性地转移金属 - 绝缘体通道，以选择性地连接和断开条和地址引线。 还提供了一种用于访问多层交叉电路内的可编程交叉点设备的方法。

    Crossbar-memory systems and methods for writing to and reading from crossbar memory junctions of crossbar-memory systems
    7.
    发明授权
    Crossbar-memory systems and methods for writing to and reading from crossbar memory junctions of crossbar-memory systems 有权
    交叉存储器系统和用于写入和读取交叉存储器系统的交叉存储器结的方法

    公开(公告)号：US07778061B2

    公开(公告)日：2010-08-17

    申请号：US11582208

    申请日：2006-10-16

    申请人： Warren Robinett ,  Philip J. Kuekes

    发明人： Warren Robinett ,  Philip J. Kuekes

    IPC分类号： G11C11/00

    CPC分类号： G11C13/02 ,  B82Y10/00 ,  G06F11/1008 ,  G06F11/1076 ,  G11C11/54 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2013/009 ,  G11C2213/16 ,  G11C2213/77 ,  G11C2213/81

    摘要： Various embodiments of the present invention are directed to crossbar-memory systems to methods for writing information to and reading information stored in such systems. In one embodiment of the present invention, a crossbar-memory system comprises a first layer of microscale signal lines, a second layer of microscale signal lines, a first layer of nanowires configured so that each first layer nanowire overlaps each first layer microscale signal line, and a second layer of nanowires configured so that each second layer nanowire overlaps each second layer microscale signal line and overlaps each first layer nanowire. The crossbar-memory system includes nonlinear-tunneling resistors configured to selectively connect first layer nanowires to first layer microscale signal lines and to selectively connect second layer nanowires to second layer microscale signal lines. The crossbar-memory system also includes nonlinear tunneling-hysteretic resistors configured to connect each first layer nanowire to each second layer nanowire at each crossbar intersection.

    摘要翻译： 本发明的各种实施例涉及交叉存储器系统，用于将信息写入和读取存储在这样的系统中的信息的方法。 在本发明的一个实施例中，交叉开关存储器系统包括微米级信号线的第一层，微米级信号线的第二层，被配置为使得每个第一层纳米线与每个第一层微米信号线重叠的第一纳米线层， 以及第二层纳米线，其被配置为使得每个第二层纳米线与每个第二层微米信号线重叠并且与每个第一层纳米线重叠。 交叉开关存储器系统包括非线性隧道电阻器，其被配置为选择性地将第一层纳米线连接到第一层微型信号线并且选择性地将第二层纳米线连接到第二层微量信号线。 交叉开关存储器系统还包括非线性隧道迟滞电阻器，其被配置为在每个交叉点交叉处将每个第一层纳米线连接到每个第二层纳米线。

    IMPLEMENTING LOGIC CIRCUITS WITH MEMRISTORS
    8.
    发明申请
    IMPLEMENTING LOGIC CIRCUITS WITH MEMRISTORS 有权
    用电磁阀实现逻辑电路

    公开(公告)号：US20140028347A1

    公开(公告)日：2014-01-30

    申请号：US13561978

    申请日：2012-07-30

    申请人： Warren Robinett ,  R. Stanley Williams

    发明人： Warren Robinett ,  R. Stanley Williams

    IPC分类号： H03K19/173

    CPC分类号： H03K19/173 ,  G11C13/0007 ,  H03K19/17712 ,  H03K19/17728

    摘要： Implementing logic with memristors may include circuitry with at least three memristors and a bias resistor in a logic cell. One of the at least three memristors is an output memristor within the logic cell and the other memristors of the at least three memristors are input memristors. Each of the at least three memristors and the bias resistor are electrically connected to voltage sources wherein each voltage applied to each of the at least three memristors and the bias resistor and resistance states of the at least three memristors determine a resistance state of the output memristor.

    摘要翻译： 使用忆阻器实现逻辑可以包括在逻辑单元中具有至少三个忆阻器和偏置电阻器的电路。 至少三个忆阻器中的一个是逻辑单元内的输出忆阻器，至少三个忆阻器的其他忆阻器是输入忆阻器。 至少三个忆阻器和偏置电阻器中的每一个电连接到电压源，其中施加到至少三个忆阻器中的每一个的每个电压和至少三个忆阻器的偏置电阻器和电阻状态确定输出忆阻器的电阻状态 。

    Mixed-scale electronic interfaces
    9.
    发明授权
    Mixed-scale electronic interfaces 失效
    混合电子接口

    公开(公告)号：US07741204B2

    公开(公告)日：2010-06-22

    申请号：US11590492

    申请日：2006-10-30

    申请人： Zhiyong Li ,  Warren Robinett

    发明人： Zhiyong Li ,  Warren Robinett

    IPC分类号： H01L21/44

    CPC分类号： G11C5/06 ,  B82B1/00 ,  B82B3/00 ,  B82Y10/00 ,  B82Y40/00 ,  G11C5/12 ,  G11C2213/81 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L51/0595 ,  Y10S977/762 ,  Y10S977/94

    摘要： Certain embodiments of the present invention are directed to a method of fabricating a mixed-scale electronic interface. A substrate is provided with a first set of conductive elements. A first layer of nanowires may be formed over the first set of conductive elements. A number of channels may be formed, with each of the channels extending diagonally through a number of the nanowires of the first layer. A number of pads may be formed, each of which is electrically interconnected with an underlying conductive element of the first set of conductive elements and one or more adjacent nanowires of the first layer of nanowires. The pads and corresponding electrically interconnected nanowires define a number of pad-interconnected-nanowire-units. Additional embodiments are directed to a method of forming a nanoimprinting mold and a method of selectively programming nanowire-to-conductive element electrical connections.

    摘要翻译： 本发明的某些实施例涉及一种制造混合比例电子接口的方法。 衬底设置有第一组导电元件。 可以在第一组导电元件上形成第一层纳米线。 可以形成多个通道，其中每个通道对角地延伸穿过第一层的多个纳米线。 可以形成多个焊盘，每个焊盘与第一组导电元件的下面的导电元件和第一纳米线层的一个或多个相邻的纳米线电互连。 焊盘和相应的电互连纳米线限定了多个衬垫互连的纳米线单元。 另外的实施例涉及形成纳米压印模具的方法和选择性地编程纳米线至导电元件电连接的方法。

    Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays
    10.
    发明授权
    Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays 失效
    基于隧道电阻器结的微米级/纳米级解复用器阵列

    公开(公告)号：US07319416B2

    公开(公告)日：2008-01-15

    申请号：US11343325

    申请日：2006-01-30

    申请人： Warren Robinett ,  Gregory S. Snider ,  Duncan Stewart ,  Joseph Straznicky

    发明人： Warren Robinett ,  Gregory S. Snider ,  Duncan Stewart ,  Joseph Straznicky

    IPC分类号： H03M7/14

    CPC分类号： G11C8/10 ,  G11C13/0023 ,  H03M13/51

    摘要： Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the present invention, an encoder-demultiplexer comprises a number of input signal lines and an encoder that generates an n-bit-constant-weight-code code-word internal address for each different input address received on the input signal lines. The encoder-demultiplexer includes n microscale signal lines on which an n-bit-constant-weight-code code-word internal address is output by the encoder, where each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address. The encoder-demultiplexer also includes a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with the n microscale signal lines via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal address.

    摘要翻译： 本发明的各种实施例涉及包括隧穿电阻器纳米线结的解复用器，以及纳米线寻址方法，用于在纳米尺度和混合尺度解复用器中可靠地寻址纳米线信号线。 在本发明的一个实施例中，编码器 - 解复用器包括多个输入信号线和一个编码器，其生成在输入信号线上接收的每个不同输入地址的n位恒权重码码字内部地址 。 编码器 - 解复用器包括n个微米级信号线，编码器输出n位恒定权重码码字内部地址，其中每个微信号线承载n位恒权重码内部地址的一位， 代码字内部地址。 编码器 - 解复用器还包括通过隧道电阻器结与n个微米级信号线互连的多个编码器 - 解复用器寻址的纳米线信号线，编码器 - 解复用器寻址的纳米线信号线每个与n比特恒权重信号线相关联， 代码字内部地址。