公开(公告)号：US07833890B2

公开(公告)日：2010-11-16

申请号：US12457366

申请日：2009-06-09

申请人： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

发明人： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

摘要翻译： 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。

公开(公告)号：US20090253255A1

公开(公告)日：2009-10-08

申请号：US12457366

申请日：2009-06-09

申请人： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

发明人： Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song ,  Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee

IPC分类号： H01L21/28

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

摘要翻译： 示例性实施例涉及半导体器件及其制造方法。 根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。 半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。 可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。 栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。 栅绝缘层可以插入在栅电极和一对鳍之间。

公开(公告)号：US07560344B2

公开(公告)日：2009-07-14

申请号：US11976004

申请日：2007-10-19

申请人： Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee ,  Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song

发明人： Suk-pil Kim ,  Yoon-dong Park ,  Jong-jin Lee ,  Won-joo Kim ,  June-mo Koo ,  Seung-hwan Song

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/792

摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.

公开(公告)号：US08013365B2

公开(公告)日：2011-09-06

申请号：US12403794

申请日：2009-03-13

申请人： Ju-hyun Ko ,  Jong-jin Lee ,  Jung-chak Ahn

发明人： Ju-hyun Ko ,  Jong-jin Lee ,  Jung-chak Ahn

IPC分类号： H01L29/66

CPC分类号： H01L27/14603

摘要： A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) includes a semiconductor substrate including a photodiode therein as a light sensing unit. A floating diffusion region of a first conductivity type is provided in the semiconductor substrate, and is configured to receive charges generated in the photodiode. A power supply voltage region of the first conductivity type is also provided in the semiconductor substrate. A reset transistor including a reset gate electrode on a surface of the substrate between the floating diffusion region and a power supply voltage region is configured to discharge charges stored in the floating diffusion region in response to a reset control signal. The reset transistor includes a channel region in the substrate extending between the floating diffusion region and the power supply voltage region such that the floating diffusion region and the power supply voltage regions define source/drain regions for the reset transistor. An impurity region is provided in a first portion of the channel region adjacent to the floating diffusion region. The impurity region has a doping such that the first portion of the channel region adjacent to the floating diffusion region has a different built-in potential than a second portion of the channel region adjacent to the power supply voltage region.

摘要翻译： 互补金属氧化物半导体（CMOS）图像传感器（CIS）包括其中包括其中的光电二极管作为光感测单元的半导体衬底。 第一导电类型的浮动扩散区域设置在半导体衬底中，并且被配置为接收在光电二极管中产生的电荷。 第一导电类型的电源电压区域也设置在半导体衬底中。 包括在浮置扩散区域和电源电压区域之间的衬底表面上的复位栅电极的复位晶体管被配置为响应于复位控制信号而放电存储在浮动扩散区域中的电荷。 所述复位晶体管包括在所述衬底中的在所述浮动扩散区域和所述电源电压区域之间延伸的沟道区域，使得所述浮动扩散区域和所述电源电压区域限定所述复位晶体管的源极/漏极区域。 杂质区设置在与浮动扩散区相邻的沟道区的第一部分中。 杂质区域具有使得与浮动扩散区域相邻的沟道区域的第一部分具有与与电源电压区域相邻的沟道区域的第二部分不同的内置电位的掺杂。

公开(公告)号：US20100021108A1

公开(公告)日：2010-01-28

申请号：US12410743

申请日：2009-03-25

申请人： Hyun-seo Kang ,  Sei-hyoung Lee ,  Kwon-seob Lim ,  Jong-jin Lee ,  Jai-sang Koh

发明人： Hyun-seo Kang ,  Sei-hyoung Lee ,  Kwon-seob Lim ,  Jong-jin Lee ,  Jai-sang Koh

IPC分类号： G02B6/26

CPC分类号： G02B6/4246 ,  G02B6/02095 ,  G02B6/29317 ,  G02B6/29323 ,  G02B6/4214

摘要： An optical waveguide device and an optical communication module are provided. In the optical waveguide device which includes a core and a cladding layer formed around the core and has one end formed to be inclined so as to refract input and output signals, the core includes therein a diffraction portion for diffracting an optical signal incident through the cladding layer to propagate straight through the core. Thus, it is possible to prevent deterioration of an optical signal coupling ratio in implementing a technique of transmitting optical signals in opposite directions.

摘要翻译： 提供光波导器件和光通信模块。 在包括芯和围绕芯部形成的包覆层的光波导器件中，其一端形成为倾斜以折射输入和输出信号，其中包括衍射部分，用于衍射通过包层入射的光信号 层直接传播通过核心。 因此，在实现相反方向上发送光信号的技术中，可以防止光信号耦合比的恶化。

公开(公告)号：US20080203507A1

公开(公告)日：2008-08-28

申请号：US11892462

申请日：2007-08-23

申请人： Kyoung-sik Moon ,  Jong-jin Lee ,  Bum-suk Kim ,  Yun-ho Jang ,  Jung-chak Ahn

发明人： Kyoung-sik Moon ,  Jong-jin Lee ,  Bum-suk Kim ,  Yun-ho Jang ,  Jung-chak Ahn

IPC分类号： H01L31/0224 ,  H01L21/00 ,  H01L31/0232

CPC分类号： H01L27/14636 ,  H01L27/14625 ,  H01L27/14685

摘要： An image sensor includes a semiconductor substrate on which a plurality of photo diodes are formed. A plurality of interlayer dielectrics are formed above the semiconductor substrate, and a plurality of metal lines are formed on each of the interlayer dielectrics. A plurality of micro lenses are formed above the uppermost one of the interlayer dielectrics. The light passing through the zoom lenses is incident on the respective micro lenses. The plurality metal lines formed on at least one of the plurality of interlayer dielectrics have the same width.

摘要翻译： 图像传感器包括其上形成有多个光电二极管的半导体基板。 在半导体衬底上形成多个层间电介质，并且在每个层间电介质上形成多个金属线。 多层微透镜形成在最上面的层间电介质之上。 通过变焦镜头的光入射到相应的微透镜上。 形成在多个层间电介质中的至少一个的多个金属线具有相同的宽度。

公开(公告)号：US20120320724A1

公开(公告)日：2012-12-20

申请号：US13488042

申请日：2012-06-04

申请人： Jong-jin Lee

发明人： Jong-jin Lee

IPC分类号： G11B20/00

CPC分类号： G11B20/10009 ,  G11B19/045 ,  G11B20/10324

摘要： An unbalanced disc determining apparatus is provided. The unbalanced disc determining apparatus includes a noise reduction unit configured to reduce noise components of a center error signal obtained from a signal configured to detect light reflected by a disc revolved by a spindle motor, and a determination unit configured to determine whether the revolving disc is unbalanced by determining whether the center error signal of which noise is reduced exceeds a reference value.

摘要翻译： 提供了一种不平衡盘确定装置。 所述不平衡盘判定装置具有：噪声降低部，被配置为减少由配置为检测由主轴电动机旋转的盘反射的光的信号获得的中心误差信号的噪声分量;以及确定单元，被配置为确定所述旋转盘是否为 通过确定哪个噪声的中心误差信号是否超过参考值而不平衡。

公开(公告)号：US20100070821A1

公开(公告)日：2010-03-18

申请号：US12557651

申请日：2009-09-11

申请人： KWAN-HO KIM ,  Jong-in Kim ,  Young-wook Jang ,  Hee-dong Shin ,  Bong-chun Kang ,  Jong-jin Lee

发明人： KWAN-HO KIM ,  Jong-in Kim ,  Young-wook Jang ,  Hee-dong Shin ,  Bong-chun Kang ,  Jong-jin Lee

IPC分类号： G06F12/00 ,  H03M13/05 ,  G06F11/10

CPC分类号： G06F11/10 ,  G06F11/1008 ,  H03M13/37 ,  H03M13/3707

摘要： A method and apparatus for detecting a free page of a memory device, and a method and apparatus for decoding an error correction code by using the method and apparatus for detecting a free page are provided. Free page data read from the memory is converted into a converted codeword for inclusion as an element of an error correction code field. The converted codeword is compared to an initially set target codeword to detect an amount of non-identical bits. A page read from the memory is determined to be a free page when the amount of non-identical bits is equal to or less than an initially set threshold value.

摘要翻译： 提供一种用于检测存储装置的自由页面的方法和装置，以及通过使用用于检测空闲页面的方法和装置来解码纠错码的方法和装置。 从存储器读取的自由页面数据被转换为转换的码字，以作为纠错码字段的元素。 将转换的码字与初始设置的目标码字进行比较，以检测不相同比特的量。 当不相同比特量等于或小于初始设置的阈值时，从存储器读取的页面被确定为空闲页面。

公开(公告)号：US5443993A

公开(公告)日：1995-08-22

申请号：US347246

申请日：1994-11-23

申请人： Won-mo Park ,  Jong-jin Lee

发明人： Won-mo Park ,  Jong-jin Lee

IPC分类号： H01L27/04 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  Y10S148/014

摘要： A method for manufacturing a capacitor for a semiconductor device, which includes the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern by patterning the first conductive layer, sequentially forming a second conductive layer and a first material layer on the entire surface of the resultant structure, forming a spacer on the sidewall of the second conductive layer by anisotropic-etching the first material layer, forming a second pattern by partially etching the second conductive layer and the first pattern, using the spacer as an etching mask, forming a third conductive layer on the entire surface of the resultant structure, forming a cylindrical storage electrode by anisotropic-etching the third conductive layer, and removing the spacer.

摘要翻译： 一种半导体器件用电容器的制造方法，其特征在于，包括以下步骤：在半导体基板上形成第一导电层，通过图案化第一导电层形成第一图案，在第二导电层上依次形成第二导电层和第一材料层 通过各向异性蚀刻第一材料层在第二导电层的侧壁上形成间隔物，通过使用间隔物作为蚀刻掩模部分蚀刻第二导电层和第一图案来形成第二图案 在所得结构的整个表面上形成第三导电层，通过各向异性蚀刻第三导电层形成圆柱形的存储电极，并且去除间隔物。

公开(公告)号：US07998861B2

公开(公告)日：2011-08-16

申请号：US12604355

申请日：2009-10-22

申请人： Jong-jin Lee ,  Hyun-seo Kang ,  Jai-sang Koh

发明人： Jong-jin Lee ,  Hyun-seo Kang ,  Jai-sang Koh

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method of manufacturing a through-via. The through-via manufacturing method includes forming a core-via hole in a wafer, forming a suction-via hole adjacent to the core-via hole in the wafer, forming a via core in the core-via hole, forming a polymer-via hole connected to the suction-via hole in the wafer, filling the polymer-via hole with polymer solution by creating a vacuum inside the polymer-via hole by drawing air out of the suction-via hole, and polishing the wafer such that the via core formed in the core-via hole is exposed.

摘要翻译： 公开了一种制造通孔的方法。 通孔制造方法包括在晶片中形成芯通孔，在晶片中形成与芯通孔相邻的吸通孔，在芯通孔中形成通孔，形成聚合物通孔 孔连接到晶片中的吸孔通孔，通过将聚合物通孔中的空气抽出吸出通孔，通过在聚合物通孔内产生真空来填充聚合物通孔，并抛光晶片，使得通孔 在芯通孔中形成的芯露出。