公开(公告)号：US08371551B2

公开(公告)日：2013-02-12

申请号：US12865834

申请日：2008-12-30

Applicant: Woo-Jin Jang

Inventor： Woo-Jin Jang

IPC: F25D23/00 ,  F16M13/00

CPC classification number: F25D23/00 ,  F25D2323/0011

Abstract: An apparatus for adjusting the level of a refrigerator includes: a main body; a guide groove formed to be level in a forward/backward direction of the main body; a movement unit inserted in the guide groove and moving in the direction in which the main body is inclined; a contact point part formed at one of both ends of the guide groove and selectively connected to the movement unit; and a notifying unit informing about whether or not the contact point part is connected. When the refrigerator is installed, an installation technician can recognize whether or not the refrigerator is installed to be level regardless of a skilled degree of the installation technician, so the installation time can be shortened and a service satisfaction of consumers can be increased.

Abstract translation: 一种用于调节冰箱水平的装置，包括：主体; 导向槽，其形成为在主体的前后方向上平坦; 移动单元，其插入所述引导槽并沿所述主体倾斜的方向移动; 接触点部分，其形成在所述引导槽的两端之一并且选择性地连接到所述移动单元; 以及通知单元，通知接点部分是否连接。 当安装冰箱时，无论安装技术人员的熟练程度如何，安装技术人员都可以识别冰箱的安装是否水平，因此可以缩短安装时间并且可以提高消费者的服务满意度。

公开(公告)号：US08373273B2

公开(公告)日：2013-02-12

申请号：US13533135

申请日：2012-06-26

Applicant: Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

Inventor： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76844 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract translation: 形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。 层间绝缘层的上表面被凹入以暴露电互连的侧壁。 电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。 在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。 该金属扩散阻挡层可以使用化学镀技术形成。

公开(公告)号：US20120267785A1

公开(公告)日：2012-10-25

申请号：US13533135

申请日：2012-06-26

Applicant: Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

Inventor： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L21/76844 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract translation: 形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。 层间绝缘层的上表面被凹入以暴露电互连的侧壁。 电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。 在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。 该金属扩散阻挡层可以使用化学镀技术形成。

公开(公告)号：US07876731B2

公开(公告)日：2011-01-25

申请号：US11321239

申请日：2005-12-29

Applicant: Woo-Jin Jang ,  Hong-Woo Lee

Inventor： Woo-Jin Jang ,  Hong-Woo Lee

IPC: H04B7/216

CPC classification number: H04B1/70735

Abstract: Disclosed herein are a method and apparatus for acquiring a code group in an asynchronous Wideband Code Division Multiple Access (WCDMA) system. A primary synchronization channel search unit achieves primary synchronization channel slot timing synchronization. Then, the 1-1 search unit and 1-2 search unit of a secondary synchronization channel receive secondary synchronization channels from first and second antennas, respectively, start correlation operations between some of the slots of the received channels and code group candidates, and transmit information about candidates having values exceeding a predetermined threshold value to a determination unit. The determination unit transmits the received information about candidates to a second search unit of the secondary synchronization channel. The second search unit of the secondary synchronization channel calculates correlation characteristics based on the received information about candidates and selects a code group candidate having a highest correlation characteristic.

Abstract translation: 本文公开了一种用于在异步宽带码分多址（WCDMA）系统中获取码组的方法和装置。 主同步信道搜索单元实现主同步信道时隙定时同步。 然后，次同步信道的1-1搜索单元和1-2搜索单元分别从第一和第二天线接收辅同步信道，开始接收信道的一些时隙和码组候选之间的相关操作，并发送 关于具有超过预定阈值的值的候选的信息给确定单元。 确定单元将接收到的关于候选的信息发送到辅同步信道的第二搜索单元。 次同步信道的第二搜索单元基于所接收的关于候选的信息计算相关特性，并选择具有最高相关特性的码组候选。

公开(公告)号：US20070210450A1

公开(公告)日：2007-09-13

申请号：US11708496

申请日：2007-02-21

Applicant: Woo-Jin Jang ,  Kwang-Myeon Park

Inventor： Woo-Jin Jang ,  Kwang-Myeon Park

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/013

Abstract: A bump may be formed by forming a diffusion barrier layer pattern over a substrate having a conductive pad; forming a seed layer over the substrate having the diffusion barrier layer pattern and the conductive pad; forming a conductive bump over the seed layer; and patterning the seed layer using the conductive bump as an etching mask.

Abstract translation: 可以通过在具有导电焊盘的衬底上形成扩散阻挡层图案来形成凸块; 在具有扩散阻挡层图案和导电焊盘的衬底上形成晶种层; 在种子层上形成导电凸块; 并使用导电凸块作为蚀刻掩模来图案化种子层。

公开(公告)号：US20060140155A1

公开(公告)日：2006-06-29

申请号：US11321239

申请日：2005-12-29

Applicant: Woo-Jin Jang ,  Hong-Woo Lee

Inventor： Woo-Jin Jang ,  Hong-Woo Lee

IPC: H04B7/216

CPC classification number: H04B1/70735

Abstract: Disclosed herein are a method and apparatus for acquiring a code group in an asynchronous Wideband Code Division Multiple Access (WCDMA) system. A primary synchronization channel search unit achieves primary synchronization channel slot timing synchronization. Then, the 1-1 search unit and 1-2 search unit of a secondary synchronization channel receive secondary synchronization channels from first and second antennas, respectively, start correlation operations between some of the slots of the received channels and code group candidates, and transmit information about candidates having values exceeding a predetermined threshold value to a determination unit. The determination unit transmits the received information about candidates to a second search unit of the secondary synchronization channel. The second search unit of the secondary synchronization channel calculates correlation characteristics based on the received information about candidates and selects a code group candidate having a highest correlation characteristic.

Abstract translation: 本文公开了一种用于在异步宽带码分多址（WCDMA）系统中获取码组的方法和装置。 主同步信道搜索单元实现主同步信道时隙定时同步。 然后，次同步信道的1-1搜索单元和1-2搜索单元分别从第一和第二天线接收辅同步信道，开始接收信道的一些时隙和码组候选之间的相关操作，并发送 关于具有超过预定阈值的值的候选的信息给确定单元。 确定单元将接收到的关于候选的信息发送到辅同步信道的第二搜索单元。 次同步信道的第二搜索单元基于所接收的关于候选的信息计算相关特性，并选择具有最高相关特性的码组候选。

公开(公告)号：US08697455B2

公开(公告)日：2014-04-15

申请号：US13415270

申请日：2012-03-08

Applicant: Kyoung-Woo Lee ,  Hong-Jae Shin ,  Woo-Jin Jang

Inventor： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Woo-Jin Jang

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.

Abstract translation: 公开了一种用于半导体器件中的蚀刻工艺的监测TEG。 TEG包括衬底上的蚀刻停止层和设置在蚀刻停止层上的要蚀刻的靶层。 要蚀刻的目标层包括通过蚀刻待蚀刻的目标层的一部分形成的第一开口部分和通过蚀刻待蚀刻的目标层的另一部分而形成的第二开口部。 第二开口部的深度比第一开口部小。 可以测量通过第一部分蚀刻工艺形成的部分接触孔的深度。

公开(公告)号：US20120231564A1

公开(公告)日：2012-09-13

申请号：US13415270

申请日：2012-03-08

Applicant: KYOUNG-WOO LEE ,  Hong-Jae Shin ,  Woo-Jin Jang

Inventor： KYOUNG-WOO LEE ,  Hong-Jae Shin ,  Woo-Jin Jang

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.

Abstract translation: 公开了一种用于半导体器件中的蚀刻工艺的监测TEG。 TEG包括衬底上的蚀刻停止层和设置在蚀刻停止层上的要蚀刻的靶层。 要蚀刻的目标层包括通过蚀刻待蚀刻的目标层的一部分形成的第一开口部分和通过蚀刻待蚀刻的目标层的另一部分而形成的第二开口部分。 第二开口部的深度比第一开口部小。 可以测量通过第一部分蚀刻工艺形成的部分接触孔的深度。

公开(公告)号：US08232200B1

公开(公告)日：2012-07-31

申请号：US13051732

申请日：2011-03-18

Applicant: Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

Inventor： Hyeok-Sang Oh ,  Woo-Jin Jang ,  Bum-Ki Moon ,  Ji-Hong Choi ,  Minseok Oh ,  Tien-Jen Cheng

IPC: H01L21/4763

CPC classification number: H01L21/76844 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76885

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract translation: 形成集成电路器件的方法包括在衬底上形成其中具有沟槽的层间绝缘层，并在沟槽中形成电互连（例如Cu镶嵌互连）。 层间绝缘层的上表面被凹入以暴露电互连的侧壁。 电绝缘的第一覆盖图案形成在层间绝缘层的凹陷的上表面和电互连的暴露的侧壁上，但是从电互连的上表面去除。 在电互连的上表面上形成金属扩散阻挡层，然而，第一覆盖图案用于阻挡电互连的侧壁上的金属扩散阻挡层的形成。 该金属扩散阻挡层可以使用化学镀技术形成。

公开(公告)号：US20110001414A1

公开(公告)日：2011-01-06

申请号：US12865834

申请日：2008-12-30

Applicant: Woo-Jin Jang

Inventor： Woo-Jin Jang

IPC: F25D23/02 ,  F16M11/24 ,  G08B21/00

CPC classification number: F25D23/00 ,  F25D2323/0011

Abstract: An apparatus for adjusting the level of a refrigerator includes: a main body; a guide groove formed to be level in a forward/backward direction of the main body; a movement unit inserted in the guide groove and moving in the direction in which the main body is inclined; a contact point part formed at one of both ends of the guide groove and selectively connected to the movement unit; and a notifying unit informing about whether or not the contact point part is connected. When the refrigerator is installed, an installation technician can recognize whether or not the refrigerator is installed to be level regardless of a skilled degree of the installation technician, so the installation time can be shortened and a service satisfaction of consumers can be increased.

Abstract translation: 一种用于调节冰箱水平的装置，包括：主体; 导向槽，其形成为在主体的前后方向上平坦; 移动单元，其插入所述引导槽并沿所述主体倾斜的方向移动; 接触点部分，其形成在所述引导槽的两端之一并且选择性地连接到所述移动单元; 以及通知单元，通知接点部分是否连接。 当安装冰箱时，无论安装技术人员的熟练程度如何，安装技术人员都可以识别冰箱是否安装成水平，因此可以缩短安装时间并且可以提高消费者的服务满意度。