-
1.发明申请Memory test system including semiconductor memory device suitable for testing an on-die termination, and method thereof 有权包括适合于测试片上终端的半导体存储器件的存储器测试系统及其方法公开(公告)号：US20080052571A1
公开(公告)日：2008-02-28
申请号：US11892846
申请日：2007-08-28
Applicant: Woo-Jin LEE , Seok-Won HWANG
Inventor： Woo-Jin LEE , Seok-Won HWANG
CPC classification number: G11C29/02 , G11C29/022 , G11C29/025
Abstract: Example embodiments relate to a memory test system having a semiconductor memory device, a coupling circuit and a tester. The semiconductor memory device may include a plurality of first output nodes and a plurality of second output nodes. The first output nodes may be connected to respective first on-die termination circuits that may not be tested, and the second output nodes may be connected to second on-die termination circuits that may be tested. The semiconductor memory device may be configured to generate test signals of the second on-die termination circuits and to provide the test signals to the second output nodes. The coupling circuit may be configured to connect the first output nodes and the second output nodes to communication channels, respectively. The tester may be configured to test a logic state of the test signals of the communication channels.
Abstract translation: 示例实施例涉及具有半导体存储器件，耦合电路和测试器的存储器测试系统。 半导体存储器件可以包括多个第一输出节点和多个第二输出节点。 第一输出节点可以连接到可能不被测试的相应的第一片上终端电路，并且第二输出节点可以连接到可以被测试的第二片上终端电路。 半导体存储器件可以被配置为产生第二片上终端电路的测试信号，并将测试信号提供给第二输出节点。 耦合电路可以被配置为分别将第一输出节点和第二输出节点连接到通信信道。 测试器可以被配置为测试通信信道的测试信号的逻辑状态。
-
2.发明申请CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE 有权在双重抽取地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法公开(公告)号：US20080225626A1
公开(公告)日：2008-09-18
申请号：US12128464
申请日：2008-05-28
Applicant: Hyun-Jin KIM , Seong-Jin JANG , Jeong-Don LIM , Kwang-Il PARK , Ho-Young SONG , Woo-Jin LEE
Inventor： Hyun-Jin KIM , Seong-Jin JANG , Jeong-Don LIM , Kwang-Il PARK , Ho-Young SONG , Woo-Jin LEE
IPC: G11C8/10
CPC classification number: G06F12/02 , G11C7/1078 , G11C7/109
Abstract: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
Abstract translation: 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。
-
3.发明申请RESIST UNDERLAYER COMPOSITION AND PROCESS OF PRODUCING INTEGRATED CIRCUIT DEVICES USING SAME 有权使用相同的底漆组合物和制造集成电路装置的方法公开(公告)号：US20130037921A1
公开(公告)日：2013-02-14
申请号：US13571751
申请日：2012-08-10
Applicant: Kwen-Woo HAN , Mi-Young KIM , Woo-Jin LEE , Han-Song LEE , Seung-Hee HONG , Sang-Kyun KIM , Jin-Wook LEE
Inventor： Kwen-Woo HAN , Mi-Young KIM , Woo-Jin LEE , Han-Song LEE , Seung-Hee HONG , Sang-Kyun KIM , Jin-Wook LEE
CPC classification number: C08L83/06 , G03F7/0752 , G03F7/091 , G03F7/094
Abstract: A resist underlayer composition, including a solvent, and an organosilane condensation polymerization product of hydrolyzed products produced from a compound represented by Chemical Formula 1, a compound represented by Chemical Formula 2, and a compound represented by Chemical Formula 3.
Abstract translation: 包含溶剂的抗蚀剂底层组合物和由化学式1表示的化合物，由化学式2表示的化合物和由化学式3表示的化合物制备的水解产物的有机硅烷缩聚产物。
-
Patent Agency Ranking
4.发明申请METHOD OF FORMING A DIELECTRIC LAYER HAVING AN ONO STRUCTURE USING AN IN-SITU PROCESS 有权使用现场处理形成具有结构的介电层的方法公开(公告)号：US20130005154A1
公开(公告)日：2013-01-03
申请号：US13444054
申请日：2012-04-11
Applicant: Woo-Jin LEE , Ji-Soon PARK , Jong-Myeong LEE , Hyun-Bae LEE
Inventor： Woo-Jin LEE , Ji-Soon PARK , Jong-Myeong LEE , Hyun-Bae LEE
IPC: H01L21/316 , H01L21/318
CPC classification number: H01L21/02164 , H01L21/0217 , H01L21/022 , H01L21/02219 , H01L21/02274 , H01L21/0228 , H01L21/0234 , H01L21/02359 , H01L21/28202 , H01L29/513 , H01L29/66825 , H01L29/7881
Abstract: A method of forming a dielectric layer, the method including sequentially forming a first oxide layer, a nitride layer, and a second oxide layer on a substrate by performing a plasma-enhanced atomic layer deposition process, wherein a first nitrogen plasma treatment is performed after forming the first oxide layer.
Abstract translation: 一种形成电介质层的方法，所述方法包括通过执行等离子体增强原子层沉积工艺在衬底上顺序地形成第一氧化物层，氮化物层和第二氧化物层，其中第一氮等离子体处理在 形成第一氧化物层。
-
5.发明申请公开(公告)号：US20120282776A1
公开(公告)日：2012-11-08
申请号：US13540111
申请日：2012-07-02
Applicant: Mi-Young KIM , Sang-Kyun KIM , Hyeon-Mo CHO , Chang-Soo WOO , Sang-Ran KOH , Hui-Chan YUN , Woo-Jin LEE , Jong-Seob KIM
Inventor： Mi-Young KIM , Sang-Kyun KIM , Hyeon-Mo CHO , Chang-Soo WOO , Sang-Ran KOH , Hui-Chan YUN , Woo-Jin LEE , Jong-Seob KIM
IPC: C09D183/06 , H01L21/311
CPC classification number: G03F7/0752 , G03F7/09 , G03F7/11
Abstract: A photoresist underlayer composition includes a solvent, and a polysiloxane resin represented by Chemical Formula 1: {(SiO1.5—Y—SiO1.5)(SiO2)y(XSiO1.5)z}(OH)e(OR1)f. [Chemical Formula 1]
Abstract translation: 光致抗蚀剂底层组合物包括溶剂和由化学式1表示的聚硅氧烷树脂：{（SiO 1.5-Y-SiO 1.5）（SiO 2）y（XSiO 1.5）z}（OH）e（OR 1）f。 [化学式1]
-
6.发明申请RESIST UNDERLAYER COMPOSITION AND PROCESS OF PRODUCING INTEGRATED CIRCUIT DEVICES USING THE SAME 有权使用相同的底层组合物和制造集成电路装置的方法公开(公告)号：US20120270981A1
公开(公告)日：2012-10-25
申请号：US13539971
申请日：2012-07-02
Applicant: Mi-Young KIM , Woo-Jin LEE , Kwen-Woo HAN , Han-Song LEE , Sang-Kyun KIM , Jong-Seob KIM
Inventor： Mi-Young KIM , Woo-Jin LEE , Kwen-Woo HAN , Han-Song LEE , Sang-Kyun KIM , Jong-Seob KIM
CPC classification number: H01L21/0332 , C08G77/80 , C09D183/04 , G03F7/0752 , G03F7/091 , H01L21/02126 , H01L21/02216 , H01L21/02282
Abstract: A resist underlayer composition includes a solvent, and an organosilane condensation polymerization product of: a compound represented by the following Chemical Formula 1, a compound represented by the following Chemical Formula 2, and a compound represented by the following Chemical Formula 3, [R1O]3Si—X [Chemical Formula 1] [R2O]3Si—R3 [Chemical Formula 2] [R4O]3Si—Si[OR5]3. [Chemical Formula 3]
Abstract translation: 抗蚀剂底层组合物包括溶剂和由以下化学式1表示的化合物，由以下化学式2表示的化合物和由以下化学式3表示的化合物的有机硅烷缩聚产物[R1O] 3Si-X [化学式1] [R2O] 3Si-R3 [化学式2] [R4O] 3Si-Si [OR5] 3。 [化学式3]
-
7.发明申请SMALL SWING SIGNAL RECEIVER FOR LOW POWER CONSUMPTION AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权用于低功耗的小触发信号接收器和包括其的半导体器件公开(公告)号：US20070188201A1
公开(公告)日：2007-08-16
申请号：US11566651
申请日：2006-12-04
Applicant: Hyun-Jin KIM , Seong-Jin JANG , Kwang-Il PARK , Woo-Jin LEE
Inventor： Hyun-Jin KIM , Seong-Jin JANG , Kwang-Il PARK , Woo-Jin LEE
IPC: H03B1/00
CPC classification number: H03K19/0013 , H03K19/018521
Abstract: A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a signal on the third node in response to the signals on the first node and the second node.
Abstract translation: 一种电路，包括耦合到第一节点和第二节点的升压电路，并且被配置为将升压的第一节点电压施加到所述第二节点; 以及反相器电路，其耦合到所述第一节点，所述第二节点和第三节点，并且被配置为响应于所述第一节点和所述第二节点上的信号而在所述第三节点上生成信号。
-
8.发明申请CIRCUIT AND METHOD FOR SAMPLING VALID COMMAND USING EXTENDED VALID ADDRESS WINDOW IN DOUBLE PUMPED ADDRESS SCHEME MEMORY DEVICE 有权在双重抽取地址方案存储器件中使用扩展有效地址窗口采样有效命令的电路和方法公开(公告)号：US20070121418A1
公开(公告)日：2007-05-31
申请号：US11560746
申请日：2006-11-16
Applicant: Hyun-Jin KIM , Seong-Jin JANG , Jeong-Don LIM , Kwang-Il PARK , Ho-Young SONG , Woo-Jin LEE
Inventor： Hyun-Jin KIM , Seong-Jin JANG , Jeong-Don LIM , Kwang-Il PARK , Ho-Young SONG , Woo-Jin LEE
IPC: G11C8/00
CPC classification number: G06F12/02 , G11C7/1078 , G11C7/109
Abstract: Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.
Abstract translation: 提供了一种用于在双抽取地址方案存储器件中使用扩展用于高速操作的有效地址窗口来对有效命令进行采样的电路和方法。 扩展有效地址窗口的方法包括：在时钟信号的第一周期输入有效的命令信号和第一地址信号; 在时钟信号的第二周期输入第二地址信号; 响应于命令信号和地址信号分别产生解码的命令信号和扩展的第一和第二内部地址信号; 以及响应于解码的命令信号来锁存和解码扩展的第一和第二内部地址信号。
-
-
-
-
-
-
-
Search Results
8
records
(took 0.024 seconds)
