公开(公告)号：US10042692B1

公开(公告)日：2018-08-07

申请号：US14869821

申请日：2015-09-29

Applicant: Xilinx, Inc.

Inventor： Sarosh I. Azad ,  Bhaarath Kumar ,  Tomai Knopp

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/263

Abstract: The disclosure describes a circuit arrangement that includes a master circuit and a slave circuit. The master circuit generates transactions, and the slave circuit generates responses to the transactions from the master circuit. A first circuit is coupled between the master circuit and the slave circuit. The first circuit determines for each transaction from the master circuit whether the slave circuit generates an expected number of responses within a timeout period. For each transaction for which the slave circuit does not generate the expected number of responses within the timeout period, the first circuit generates and transmits the expected number of responses to the master circuit.

公开(公告)号：US11581881B1

公开(公告)日：2023-02-14

申请号：US17405854

申请日：2021-08-18

Applicant: XILINX, INC.

Inventor： Sarosh I. Azad ,  Benson Chau ,  Tomai Knopp

IPC: H03K5/02 ,  H03K23/60 ,  H03K19/20 ,  H03K19/173 ,  H03K5/00

Abstract: An integrated circuit (IC) for clock and phase aligning and synchronization between physical (PHY) layers and a communications controller is provided. The IC includes a clock multiplier configured to multiply a frequency of the clock signal from a plurality of PHY layers to match a frequency of a clock signal of the controller, wherein the clock signal from the plurality of PHY layers is less than the frequency of the clock signal of the controller. IC support circuitry is configured to provide the multiplied clock signal to the controller. The IC includes a first clock divider configured to divide the frequency of the multiplied clock signal and to output the divided clock signal to the controller. The IC includes a phase alignment circuit configured to align phases of one or more data signals based on a phase of the clock signal and a phase of the multiplied clock signal.

公开(公告)号：US10169177B1

公开(公告)日：2019-01-01

申请号：US15802274

申请日：2017-11-02

Applicant: Xilinx, Inc.

Inventor： Banadappa V Shivaray ,  Pranjal Chauhan ,  Pramod Surathkal ,  Alex S. Warshofsky ,  Tomai Knopp ,  Soumitra Kumar Bhowmick ,  Ahmad R. Ansari

IPC: G06F11/22 ,  G06F17/50 ,  H03K19/003

Abstract: Embodiments herein describe a methodology for performing non-destructive LBIST when booting an integrated circuit (IC). In one embodiment, when powered on, the IC begins the boot process (e.g., a POST) which is then paused to perform LBIST. However, instead of corrupting or destroying the boot mode state of the IC, the LBIST is non-destructive. That is, after LBIST is performed, the booting process can be resumed in the same state as when LBIST began.

公开(公告)号：US11281618B2

公开(公告)日：2022-03-22

申请号：US14530561

申请日：2014-10-31

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Tomai Knopp

IPC: G06F13/42 ,  G06F13/16 ,  G06F12/0831 ,  G06F12/0804 ,  G06F12/0888 ,  G06F13/40

Abstract: A system is disclosed that includes a first communication circuit that communicates data over a first data port using a first communication protocol. The system also includes a second communication circuit that communicates data over a second data port using a second communication protocol. The second communication protocol processes read and write requests in an order that the read and write requests are received. A bridge circuit is configured to communicate data between the first data port of the first communication circuit and the second data port of the second communication circuit. The bridge circuit is configured to communicate non-posted writes to the second communication circuit via a buffer circuit and communicate posted writes to the second communication circuit via a communication path that bypasses the buffer circuit.

公开(公告)号：US20160124891A1

公开(公告)日：2016-05-05

申请号：US14530561

申请日：2014-10-31

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Tomai Knopp

IPC: G06F13/42 ,  G06F12/08 ,  G06F13/16

CPC classification number: G06F13/4282 ,  G06F12/0804 ,  G06F12/0833 ,  G06F12/0888 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/4036 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system is disclosed that includes a first communication circuit that communicates data over a first data port using a first communication protocol. The system also includes a second communication circuit that communicates data over a second data port using a second communication protocol. The second communication protocol processes read and write requests in an order that the read and write requests are received. A bridge circuit is configured to communicate data between the first data port of the first communication circuit and the second data port of the second communication circuit. The bridge circuit is configured to communicate non-posted writes to the second communication circuit via a buffer circuit and communicate posted writes to the second communication circuit via a communication path that bypasses the buffer circuit.

Abstract translation: 公开了一种包括通过第一通信协议在第一数据端口上传送数据的第一通信电路的系统。 该系统还包括通过第二通信协议在第二数据端口上传送数据的第二通信电路。 第二通信协议按照接收到读取和写入请求的顺序处理读取和写入请求。 桥电路被配置为在第一通信电路的第一数据端口和第二通信电路的第二数据端口之间传送数据。 桥接电路被配置为经由缓冲电路将未发布的写入传送到第二通信电路，并且经由绕过缓冲电路的通信路径将发布的写入传送到第二通信电路。

公开(公告)号：US10861578B1

公开(公告)日：2020-12-08

申请号：US16718535

申请日：2019-12-18

Applicant: Xilinx, Inc.

Inventor： Roger D. Flateau, Jr. ,  Tomai Knopp

IPC: G11C29/44 ,  G11C29/00 ,  G11C29/24 ,  G11C29/14 ,  G11C29/04

Abstract: A device includes a plurality of memory components with redundant columns associated therewith, a sub-block controller, and a volatile memory. The sub-block controller generates a repair vector, during manufacture testing mode. The repair vector is associated with the plurality of memory components and is generated responsive to detecting a defect within a column of the plurality of memory components. No repair vector is generated responsive to detecting no defect within a column of the plurality of memory components. The volatile memory receives and stores the repair vector in a nonvolatile memory component, during the manufacture testing mode. The volatile memory receives the repair vector from the nonvolatile memory component if the repair vector was generated during the manufacture testing mode, at startup mode, and provides it to the sub-block controller. The sub-block controller loads a repair data into the plurality of memory components based on the repair vector.

公开(公告)号：US09495239B1

公开(公告)日：2016-11-15

申请号：US14466845

申请日：2014-08-22

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Bradley L. Taylor ,  Ahmad R. Ansari ,  Tomai Knopp

IPC: G06F11/07 ,  G06F11/14

CPC classification number: G06F11/0793 ,  G06F11/0706 ,  G06F11/0772 ,  G06F11/142 ,  G06F11/1441

Abstract: A method for operating a programmable IC is disclosed. A set of circuits specified by a set of configuration data is operated in a set of programmable resources. In response to one of a set of status signals indicating an error, a value indicative of an error is stored in a respective one of a plurality of error status registers. The values stored in the plurality of error status registers are provided to an error handling circuit included in the set of circuits specified by the set of configuration data and operated in the programmable resources. At least one error handling process is performed by the error handling circuit as a function of values stored in the plurality of error status registers.

Abstract translation: 公开了一种用于操作可编程IC的方法。 由一组配置数据指定的一组电路在一组可编程资源中操作。 响应于指示错误的一组状态信号中的一个，指示错误的值被存储在多个错误状态寄存器中的相应一个中。 存储在多个错误状态寄存器中的值被提供给由该组配置数据指定并在可编程资源中操作的电路集合中包括的错误处理电路。 由错误处理电路执行至少一个错误处理过程作为存储在多个错误状态寄存器中的值的函数。

公开(公告)号：US09465766B1

公开(公告)日：2016-10-11

申请号：US14065804

申请日：2013-10-29

Applicant: Xilinx, Inc.

Inventor： Tomai Knopp ,  Sarosh I. Azad ,  Bhaarath Kumar

IPC: G06F13/36 ,  G06F13/42

CPC classification number: G06F13/42

Abstract: An apparatus for communication using a master-slave communication protocol includes a master circuit and a slave circuit configured to communicate with each other using a master-slave communication protocol. The apparatus also includes an interface circuit coupled to the master and slave circuits. In response to a first control signal having a first value, the interface circuit forwards messages received from the master circuit to the slave circuit and forwards responses received from the slave circuit to the master circuit. In response to the first control signal having a second value, the interface circuit prevents messages received from the master circuit from being forwarded from the master circuit to the slave circuit.

Abstract translation: 使用主从通信协议的通信装置包括主电路和被配置为使用主 - 从通信协议彼此通信的从电路。 该装置还包括耦合到主电路和从电路的接口电路。 响应于具有第一值的第一控制信号，接口电路将从主电路接收的消息转发到从电路，并将从从电路接收的响应转发给主电路。 响应于具有第二值的第一控制信号，接口电路防止从主电路接收的消息从主电路转发到从电路。