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    Deposition-plasma cure cycle process to enhance film quality of silicon dioxide
    2.
    发明授权
    Deposition-plasma cure cycle process to enhance film quality of silicon dioxide 有权
    沉积 - 等离子体固化循环过程，以提高二氧化硅的膜质量

    公开(公告)号：US07902080B2

    公开(公告)日：2011-03-08

    申请号：US11753968

    申请日：2007-05-25

    申请人： Xiaolin Chen ,  Srinivas D. Nemani ,  Shankar Venkataraman

    发明人： Xiaolin Chen ,  Srinivas D. Nemani ,  Shankar Venkataraman

    IPC分类号： H01L21/302

    CPC分类号： C23C16/045 ,  C23C16/402 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/31633

    摘要： Methods of filling a gap on a substrate with silicon oxide are described. The methods may include the steps of introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber, reacting the precursors to form a first silicon oxide layer in the gap on the substrate, and etching the first silicon oxide layer to reduce the carbon content in the layer. The methods may also include forming a second silicon oxide layer on the first layer, and etching the second layer to reduce the carbon content in the second layer. The silicon oxide layers are annealed after the gap is filled.

    摘要翻译： 描述了用氧化硅填充衬底上的间隙的方法。 所述方法可以包括以下步骤：将有机硅前体和氧前体引入沉积室，使前体反应以在衬底上的间隙中形成第一氧化硅层，并蚀刻第一氧化硅层以还原碳 内容在图层中。 所述方法还可以包括在第一层上形成第二氧化硅层，并蚀刻第二层以降低第二层中的碳含量。 在填充间隙之后对氧化硅层进行退火。

    Process sequence for formation of patterned hard mask film (RFP) without need for photoresist or dry etch
    3.
    发明授权
    Process sequence for formation of patterned hard mask film (RFP) without need for photoresist or dry etch 有权
    用于形成图案化硬掩模膜（RFP）的工艺顺序，无需光致抗蚀剂或干蚀刻

    公开(公告)号：US08153348B2

    公开(公告)日：2012-04-10

    申请号：US12034000

    申请日：2008-02-20

    申请人： Srinivas D. Nemani ,  Shankar Venkataraman ,  Ellie Y. Yieh

    发明人： Srinivas D. Nemani ,  Shankar Venkataraman ,  Ellie Y. Yieh

    IPC分类号： G03F7/26

    CPC分类号： G03F7/0757 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31612 ,  H01L21/6719 ,  H01L21/67207

    摘要： Method and systems for patterning a hardmask film using ultraviolet light is disclosed according to one embodiment of the invention. Embodiments of the present invention alleviate the processing problem of depositing and etching photoresist in order to produce a hardmask pattern. A hardmask layer, such as, silicon oxide, is first deposited on a substrate within a deposition chamber. In some cases, the hardmask layer is baked or annealed following deposition. After which, portions of the hardmask layer are exposed with ultraviolet light. The ultraviolet light produces a pattern of exposed and unexposed portions of hardmask material. Following the exposure, an etching process, such as a wet etch, may occur that removes the unexposed portions of the hardmask. Following the etch, the hardmask may be annealed, baked or subjected to a plasma treatment.

    摘要翻译： 根据本发明的一个实施方案公开了使用紫外光图案化硬掩膜的方法和系统。 本发明的实施例减轻了沉积和蚀刻光刻胶的处理问题，以产生硬掩模图案。 首先将诸如氧化硅的硬掩模层沉积在沉积室内的衬底上。 在一些情况下，硬掩模层在沉积之后被烘烤或退火。 之后，硬掩模层的一部分用紫外线照射。 紫外光产生硬掩模材料的暴露和未曝光部分的图案。 曝光后，可能会发生腐蚀过程，例如湿蚀刻，从而去除硬掩模的未曝光部分。 在蚀刻之后，可以对硬掩模进行退火，烘烤或进行等离子体处理。

    Plasma enhanced CVD low k carbon-doped silicon oxide film deposition using VHF-RF power
    6.
    发明授权
    Plasma enhanced CVD low k carbon-doped silicon oxide film deposition using VHF-RF power 失效
    使用VHF-RF功率的等离子体增强CVD低k碳掺杂氧化硅膜沉积

    公开(公告)号：US06797643B2

    公开(公告)日：2004-09-28

    申请号：US10279367

    申请日：2002-10-23

    申请人： Juan Carlos Rocha-Alvarez ,  Maosheng Zhao ,  Ying Yu ,  Shankar Venkataraman ,  Srinivas D. Nemani ,  Li-Qun Xia

    发明人： Juan Carlos Rocha-Alvarez ,  Maosheng Zhao ,  Ying Yu ,  Shankar Venkataraman ,  Srinivas D. Nemani ,  Li-Qun Xia

    IPC分类号： H01L2131

    CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31633

    摘要： A method of depositing a low dielectric constant film on a substrate. In one embodiment, the method includes the steps of positioning the substrate in a deposition chamber, providing a gas mixture to the deposition chamber, in which the gas mixture is comprised of one or more cyclic organosilicon compounds, one or more aliphatic compounds and one or more oxidizing gases. The method further includes reacting the gas mixture in the presence of an electric field to form the low dielectric constant film on the semiconductor substrate. The electric field is generated using a very high frequency power having a frequency in a range of about 20 MHz to about 100 MHz.

    摘要翻译： 在基板上沉积低介电常数膜的方法。 在一个实施例中，该方法包括以下步骤：将基板定位在沉积室中，为沉积室提供气体混合物，其中气体混合物由一种或多种环状有机硅化合物，一种或多种脂族化合物和一种或多种脂族化合物组成， 更多的氧化气体。 该方法还包括在存在电场的情况下使气体混合物反应以在半导体衬底上形成低介电常数膜。 使用频率在约20MHz至约100MHz范围内的非常高频率的功率产生电场。

    POST DEPOSITION PLASMA TREATMENT TO INCREASE TENSILE STRESS OF HDP-CVD SIO2
    8.
    发明申请
    POST DEPOSITION PLASMA TREATMENT TO INCREASE TENSILE STRESS OF HDP-CVD SIO2 失效
    后沉积等离子体处理以提高HDP-CVD SIO2的拉伸应力

    公开(公告)号：US20090035918A1

    公开(公告)日：2009-02-05

    申请号：US12252260

    申请日：2008-10-15

    申请人： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

    发明人： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

    IPC分类号： H01L21/76

    CPC分类号： H01L21/3105 ,  C23C16/402 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612

    摘要： Methods of forming a dielectric layer where the tensile stress of the layer is increased by a plasma treatment at an elevated position are described. In one embodiment, oxide and nitride layers are deposited on a substrate and patterned to form an opening. A trench is etched into the substrate. The substrate is transferred into a chamber suitable for dielectric deposition. A dielectric layer is deposited over the substrate, filling the trench and covering mesa regions adjacent to the trench. The substrate is raised to an elevated position above the substrate support and exposed to a plasma which increases the tensile stress of the substrate. The substrate is removed from the dielectric deposition chamber, and portions of the dielectric layer are removed so that the dielectric layer is even with the topmost portion of the nitride layer. The nitride and pad oxide layers are removed to form the STI structure.

    摘要翻译： 描述了通过在升高的位置处的等离子体处理来增加层的拉伸应力的电介质层的形成方法。 在一个实施例中，将氧化物和氮化物层沉积在衬底上并图案化以形成开口。 沟槽被蚀刻到衬底中。 将基底转移到适合于电介质沉积的室中。 介电层沉积在衬底上，填充沟槽并覆盖与沟槽相邻的台面区域。 将衬底升高到衬底支撑件上方的升高位置并暴露于等离子体，这增加了衬底的拉伸应力。 从电介质沉积室取出基板，除去介质层的部分，使得介质层与氮化物层的最上部分均匀。 去除氮化物层和衬垫氧化物层以形成STI结构。

    Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2
    9.
    发明授权
    Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2 失效
    后沉积等离子体处理以增加HDP-CVD SIO2的拉伸应力

    公开(公告)号：US07465680B2

    公开(公告)日：2008-12-16

    申请号：US11221303

    申请日：2005-09-07

    申请人： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

    发明人： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/3105 ,  C23C16/402 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612

    摘要： A plasma treatment process for increasing the tensile stress of a silicon wafer is described. Following deposition of a dielectric layer on a substrate, the substrate is lifted to an elevated position above the substrate receiving surface and exposed to a plasma treatment process which treats both the top and bottom surface of the wafer and increases the tensile stress of the deposited layer. Another embodiment of the invention involves biasing of the substrate prior to plasma treatment to bombard the wafer with plasma ions and raise the temperature of the substrate. In another embodiment of the invention, a two-step plasma treatment process can be used where the substrate is first exposed to a plasma at a processing position directly after deposition, and then raised to an elevated position where both the top and bottom of the wafer are exposed to the plasma.

    摘要翻译： 描述了用于增加硅晶片的拉伸应力的等离子体处理工艺。 在基底上沉积介电层之后，将衬底提升到衬底接收表面上方的升高位置并暴露于等离子体处理工艺，其处理晶片的顶表面和底表面并增加沉积层的拉伸应力 。 本发明的另一实施例涉及在等离子体处理之前偏压衬底以用等离子体离子轰击晶片并提高衬底的温度。 在本发明的另一个实施例中，可以使用两步等离子体处理工艺，其中首先在沉积后直接在处理位置处暴露于等离子体，然后升高到晶片的顶部和底部两者的升高位置 暴露于等离子体。

    Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2
    10.
    发明授权
    Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2 失效
    后沉积等离子体处理以增加HDP-CVD SIO2的拉伸应力

    公开(公告)号：US07745351B2

    公开(公告)日：2010-06-29

    申请号：US12252260

    申请日：2008-10-15

    申请人： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

    发明人： Xiaolin Chen ,  Srinivas D. Nemani ,  DongQing Li ,  Jeffrey C. Munro ,  Marlon E. Menezes

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/3105 ,  C23C16/402 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612

    摘要： Methods of forming a dielectric layer where the tensile stress of the layer is increased by a plasma treatment at an elevated position are described. In one embodiment, oxide and nitride layers are deposited on a substrate and patterned to form an opening. A trench is etched into the substrate. The substrate is transferred into a chamber suitable for dielectric deposition. A dielectric layer is deposited over the substrate, filling the trench and covering mesa regions adjacent to the trench. The substrate is raised to an elevated position above the substrate support and exposed to a plasma which increases the tensile stress of the substrate. The substrate is removed from the dielectric deposition chamber, and portions of the dielectric layer are removed so that the dielectric layer is even with the topmost portion of the nitride layer. The nitride and pad oxide layers are removed to form the STI structure.

    摘要翻译： 描述了通过在升高的位置处的等离子体处理来增加层的拉伸应力的电介质层的形成方法。 在一个实施例中，将氧化物和氮化物层沉积在衬底上并图案化以形成开口。 沟槽被蚀刻到衬底中。 将基底转移到适合于电介质沉积的室中。 介电层沉积在衬底上，填充沟槽并覆盖与沟槽相邻的台面区域。 将衬底升高到衬底支撑件上方的升高位置并暴露于等离子体，这增加了衬底的拉伸应力。 从电介质沉积室取出基板，除去介质层的部分，使得介质层与氮化物层的最上部分均匀。 去除氮化物层和衬垫氧化物层以形成STI结构。