公开(公告)号：US20170271016A1

公开(公告)日：2017-09-21

申请号：US15611451

申请日：2017-06-01

申请人： YOON-HEE CHOI ,  SUNGYEON LEE ,  SANG-HYUN JOO

发明人： YOON-HEE CHOI ,  SUNGYEON LEE ,  SANG-HYUN JOO

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C7/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time. The program loop includes a programming step for programming selected memory cells among memory cells and a verifying step for verifying whether the selected memory cells are program-passed or not. In programming the selected memory cells, a level of a voltage being applied to a common source line connected to the memory cells in common may be changed. Thus, in a program operation, power consumption which is needed to charge-discharge the common source line can be decreased while increasing boosting efficiency.

公开(公告)号：US20170169897A1

公开(公告)日：2017-06-15

申请号：US15292417

申请日：2016-10-13

申请人： HO-JUN LEE ,  SANG-HYUN JOO

发明人： HO-JUN LEE ,  SANG-HYUN JOO

IPC分类号： G11C16/34 ,  G11C16/16 ,  G11C16/08 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C16/3495 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/26 ,  G11C29/50004 ,  G11C2029/0409 ,  G11C2029/1202 ,  G11C2029/1204

摘要： A method of operating a non-volatile memory device includes selecting a first select transistor from among a plurality of select transistors included in a NAND string, and performing a check operation on a first threshold voltage of the first select transistor. The check operation includes comparing the first threshold voltage with a first lower-limit reference voltage level, and performing a program operation on the first select transistor when the first threshold voltage is lower than the first lower-limit reference voltage level. When the first threshold voltage is equal to or higher than the first lower-limit reference voltage level, the check operation on the first threshold voltage is ended.

公开(公告)号：US20130083607A1

公开(公告)日：2013-04-04

申请号：US13608030

申请日：2012-09-10

申请人： SANG-HYUN JOO ,  KIWHAN SONG ,  JU SEOK LEE ,  KIHWAN CHOI

发明人： SANG-HYUN JOO ,  KIWHAN SONG ,  JU SEOK LEE ,  KIHWAN CHOI

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C2211/563

摘要： A soft-decision read method of a nonvolatile memory device includes receiving a soft-decision read command, applying a read voltage to a selected word line, pre-charging bit lines respectively connected to selected memory cells of the selected word line, continuously sensing states of the selected memory cells. The pre-charged voltages of the bit lines and the read voltage supplied to the selected word line are not varied during the sensing states of the selected memory cells.

摘要翻译： 非易失性存储器件的软判决读取方法包括：接收软判决读命令，将读电压施加到所选择的字线，对分别连接到所选字线的选定存储单元的位线进行预充电，连续检测状态 的所选存储单元。 提供给所选字线的位线的预充电电压和读取电压在所选存储单元的感测状态期间不改变。

公开(公告)号：US20170206124A1

公开(公告)日：2017-07-20

申请号：US15405339

申请日：2017-01-13

申请人： BONG-SOON LIM ,  SANG-HYUN JOO ,  KEE-HO JUNG

发明人： BONG-SOON LIM ,  SANG-HYUN JOO ,  KEE-HO JUNG

IPC分类号： G06F11/07 ,  G11C11/56 ,  G11C16/34

CPC分类号： G06F11/076 ,  G06F11/0727 ,  G06F11/0787 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/3459

摘要： A non-volatile memory includes a page buffer array in which page buffers are arranged in a matrix form. A method of operating the non-volatile memory includes selecting columns from among multiple columns of the page buffer array, and counting fail bits stored in page buffers included in the selected columns.

公开(公告)号：US20170075757A1

公开(公告)日：2017-03-16

申请号：US15061349

申请日：2016-03-04

申请人： JAE-WOO IM ,  SANG-HYUN JOO

发明人： JAE-WOO IM ,  SANG-HYUN JOO

IPC分类号： G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC分类号： G06F11/1068 ,  G11C29/52

摘要： A memory cell array includes memory cells that are formed in vertical channels extended in a vertical direction with respect to a substrate. The vertical channels are arranged in a zig-zag manner in parallel to the first direction. A read-write circuit is connected to the memory cells via bit lines. An address decoder decodes an address to provide decoded address signals to the read-write circuit. The memory cells include outer cells and inner cells. A distance between one of the outer cells and a common source node is smaller than a distance between one of the inner cells and the common source node. Data of the memory cells are distributed among ECC sectors and a data input-output order of the memory cells is arranged such that each ECC sector has substantially the same number of the outer cells and the inner cells. Each ECC sector corresponds to an ECC operation unit.

摘要翻译： 存储单元阵列包括形成在相对于衬底沿垂直方向延伸的垂直通道中的存储单元。 垂直通道平行于第一方向以锯齿形排列。 读写电路通过位线连接到存储单元。 地址解码器解码地址以将解码的地址信号提供给读写电路。 记忆单元包括外细胞和内细胞。 外部单元之一和公共源节点之间的距离小于内部单元和公共源节点之间的距离。 存储器单元的数据被分配在ECC扇区中，并且存储单元的数据输入 - 输出顺序被布置成使得每个ECC扇区具有基本上相同数量的外单元和内单元。 每个ECC扇区对应于ECC操作单元。

公开(公告)号：US20130336058A1

公开(公告)日：2013-12-19

申请号：US13795750

申请日：2013-03-12

申请人： SANG-HYUN JOO ,  IL-HAN PARK ,  KI-WHAN SONG

发明人： SANG-HYUN JOO ,  IL-HAN PARK ,  KI-WHAN SONG

IPC分类号： G11C16/34

CPC分类号： G11C16/3418 ,  G11C11/5628 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26

摘要： A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating node, and a memory cell configured to store multi-bit data. The nonvolatile memory device performs a refresh operation on the first dynamic latch where externally supplied first single bit data is stored in the first dynamic latch, performs a refresh operation on the second dynamic latch where externally supplied second single bit data is stored in the second dynamic latch, and programs the memory cell using the data stored in the first and second dynamic latches after the first and second single bit data are stored in the respective first and second dynamic latches.

摘要翻译： 非易失性存储器件包括非易失性存储器芯片，其包括静态锁存器，通过浮动节点接收存储在静态锁存器中的数据的第一和第二动态锁存器以及被配置为存储多位数据的存储器单元。 非易失性存储器件对第一动态锁存器执行刷新操作，其中外部提供的第一单位数据被存储在第一动态锁存器中，对外部提供的第二单位数据存储在第二动态锁存器中的第二动态锁存器执行刷新操作 在第一和第二单个位数据存储在相应的第一和第二动态锁存器中之后，使用存储在第一和第二动态锁存器中的数据对存储器单元进行锁存和编程。

公开(公告)号：US20130117500A1

公开(公告)日：2013-05-09

申请号：US13553845

申请日：2012-07-20

申请人： SANG-HYUN JOO ,  SANGYONG YOON

发明人： SANG-HYUN JOO ,  SANGYONG YOON

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0035 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/349 ,  G11C2211/5641 ,  G11C2211/5644

摘要： A memory managing method is provided for a memory system, including a nonvolatile memory device and a memory controller controlling the nonvolatile memory device. The memory managing method includes determining whether a program-erase number of a memory block in the nonvolatile memory device reaches a first reference value; managing a life of the memory block according to a first memory managing method when the program-erase number of the memory block is determined to be less than the first reference value; and managing the life of the memory block according to a second memory managing method different from the first memory managing method when the program-erase number of the memory block is determined to be greater than the first reference value.

摘要翻译： 提供了一种用于存储器系统的存储器管理方法，包括非易失性存储器件和控制非易失性存储器件的存储器控​​制器。 存储器管理方法包括确定非易失性存储器件中的存储块的编程擦除次数是否达到第一参考值; 当存储块的编程擦除次数被确定为小于第一参考值时，根据第一存储器管理方法管理存储块的寿命; 以及当所述存储器块的所述编程擦除次数被确定为大于所述第一参考值时，根据与所述第一存储器管理方法不同的第二存储器管理方法来管理所述存储块的寿命。