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    Nonvolatile semiconductor memory device with improved reliability and operation speed
    1.
    发明授权
    Nonvolatile semiconductor memory device with improved reliability and operation speed 失效
    非易失性半导体存储器件具有提高的可靠性和运行速度

    公开(公告)号：US06388921B1

    公开(公告)日：2002-05-14

    申请号：US09695224

    申请日：2000-10-25

    申请人： Yasuhiro Yamamoto ,  Tomoshi Futatsuya ,  Yoshikazu Miyawaki

    发明人： Yasuhiro Yamamoto ,  Tomoshi Futatsuya ,  Yoshikazu Miyawaki

    IPC分类号： G11C1604

    CPC分类号： H01L27/11521 ,  G11C16/0416 ,  G11C16/22 ,  H01L27/115 ,  H01L27/11524

    摘要： A memory transistor for a lock bit, holding information on whether a memory block can be erased/reprogrammed, is provided in the same column as that of a plurality of dummy cells. Since a sub bit line for reading the lock bit is electrically isolated from a sub bit line for dummy cell, accurate lock-bit reading is possible even when the dummy cell is over erased. Thus, a nonvolatile semiconductor memory device advantageous in reliability and operation time can be provided.

    摘要翻译： 在与多个虚拟单元的列相同的列中提供了用于锁定位的存储晶体管，用于保存有关存储块是否可被擦除/重新编程的信息。 由于用于读取锁定位的子位线与用于虚拟单元的子位线电隔离，因此即使当虚设单元被擦除时，也可以进行精确的锁定位读取。 因此，可以提供有利于可靠性和操作时间的非易失性半导体存储器件。

    Nonvolatile semiconductor memory device with a row redundancy circuit
    2.
    发明授权
    Nonvolatile semiconductor memory device with a row redundancy circuit 失效
    具有行冗余电路的非易失性半导体存储器件

    公开(公告)号：US5602778A

    公开(公告)日：1997-02-11

    申请号：US468393

    申请日：1995-06-06

    申请人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    发明人： Tomoshi Futatsuya ,  Masaaki Mihara ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Shinichi Kobayashi ,  Minoru Ohkawa

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/06 ,  G11C16/08 ,  G11C29/00 ,  G11C29/04 ,  G11C11/34

    CPC分类号： G11C29/804 ,  G11C16/08 ,  G11C29/82 ,  G11C29/848

    摘要： A collective erasure type nonvolatile semiconductor memory device which allows use of redundant structure to word lines is provided. A row address buffer having address converting function simultaneously selects a plurality of physically adjacent word lines from a memory array in programming before erasure. Programming before erasure is effected on the memory cells on the simultaneously selected word lines. Even when physically adjacent word lines are short-circuited between each other, programming high voltage can be transmitted to the defective word lines, as these word lines are selected simultaneously. Therefore, the memory cells on the defective word lines can be programmed before erasure, so that over erasure at the time of collective erasing operation can be prevented. Thus, redundant structure for replacing defecting word lines by spare word lines can be utilized.

    摘要翻译： 提供了允许对字线使用冗余结构的集体擦除型非易失性半导体存储器件。 具有地址转换功能的行地址缓冲器在擦除之前在编程中同时从存储器阵列中选择多个物理上相邻的字线。 擦除之前的编程对同时选择的字线上的存储单元进行。 即使当物理上相邻的字线彼此短路时，由于这些字线被同时选择，编程高电压也可被传送到有缺陷的字线。 因此，可以在擦除之前对缺陷字线上的存储单元进行编程，从而可以防止在集体擦除操作时的过度擦除。 因此，可以利用用备用字线代替缺陷字线的冗余结构。

    Nonvolatile semiconductor memory device capable of erasing by a word line unit
    3.
    发明授权
    Nonvolatile semiconductor memory device capable of erasing by a word line unit 失效
    能够通过字线单元擦除的非易失性半导体存储器件

    公开(公告)号：US5402382A

    公开(公告)日：1995-03-28

    申请号：US942887

    申请日：1992-09-10

    申请人： Yoshikazu Miyawaki ,  Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Tomoshi Futatsuya

    发明人： Yoshikazu Miyawaki ,  Yasushi Terada ,  Takeshi Nakayama ,  Shinichi Kobayashi ,  Tomoshi Futatsuya

    IPC分类号： H01L21/8247 ,  G11C16/16 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

    CPC分类号： G11C16/16

    摘要： A nonvolatile semiconductor memory device has a plurality of memory cells, which are arranged in a matrix form having rows and columns and each have floating a gate for holding an information charge, a plurality of bit lines, a plurality of word lines, a plurality of source lines, and a high voltage generator for generating a negative high voltage. The high voltage generator is connected to each word line and has a capacitor to which a predetermined clock is applied in response to a signal for selecting word lines. The semiconductor memory device further comprises an erasing device, which applies the negative high voltage generated by, the high voltage generator to the word line selected by the selection signal in the erasing operation. The erasing device grounds the source line connected to the source of the corresponding memory cell.

    摘要翻译： 非易失性半导体存储器件具有多个存储单元，它们以具有行和列的矩阵形式布置，并且各自具有用于保持信息电荷的栅极，多个位线，多个字线，多个 源极线和用于产生负高电压的高压发生器。 高电压发生器连接到每个字线，并且响应于用于选择字线的信号，具有施加预定时钟的电容器。 半导体存储器件还包括擦除器件，其在擦除操作中将由高电压发生器产生的负高电压施加到由选择信号选择的字线。 擦除装置将连接到相应存储单元的源的源极线接地。

    Internal voltage generator for a non-volatile semiconductor memory device
    4.
    发明授权
    Internal voltage generator for a non-volatile semiconductor memory device 失效
    用于非易失性半导体存储器件的内部电压发生器

    公开(公告)号：US5371705A

    公开(公告)日：1994-12-06

    申请号：US066300

    申请日：1993-05-24

    申请人： Takeshi Nakayama ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Shinichi Kobayashi

    发明人： Takeshi Nakayama ,  Yasushi Terada ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya ,  Shinichi Kobayashi

    IPC分类号： G05F3/24 ,  G11C5/14 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  G11C17/00 ,  H02M3/07 ,  H03K19/00 ,  G11C7/00

    CPC分类号： G11C5/143 ,  G11C16/12 ,  G11C16/30

    摘要： The semiconductor device includes a voltage generator for generating selectively a signal of a first level or a second level onto a first supply line, and a voltage converter using voltage signals on the first supply line and a second supply line for producing a signal of the voltage level on the first or the second supply line in accordance with an input signal, and a voltage level shifter for detecting the level of the voltage on the first supply line to shift in voltage level a signal on the second power supply line toward the first level when the voltage on the first supply line approaches the first level. The difference of the voltages on the first and second supply lines can be reduced to improve the break-down characteristics of a transistor included in the voltage converter, resulting in a reliable semiconductor device.

    摘要翻译： 半导体器件包括用于在第一电源线上选择性地产生第一电平或第二电平的信号的电压发生器，以及使用第一电源线上的电压信号的电压转换器和用于产生电压信号的第二电源线 根据输入信号在第一或第二供电线上的电平;以及电压电平移位器，用于检测第一电源线上的电压电平，使电压电平将第二电源线上的信号移向第一电平 当第一电源线上的电压接近第一电平时。 可以减小第一和第二电源线上的电压差，以改善包括在电压转换器中的晶体管的分解特性，从而获得可靠的半导体器件。

    Nonvolatile memory with background operation function
    6.
    发明授权
    Nonvolatile memory with background operation function 失效
    具有背景操作功能的非易失性存储器

    公开(公告)号：US06483748B2

    公开(公告)日：2002-11-19

    申请号：US09729415

    申请日：2000-12-05

    申请人： Tomoshi Futatsuya ,  Yoshikazu Miyawaki

    发明人： Tomoshi Futatsuya ,  Yoshikazu Miyawaki

    IPC分类号： G11C1604

    CPC分类号： G11C7/1069 ,  G11C7/06 ,  G11C7/1051 ,  G11C7/1078 ,  G11C16/26

    摘要： An external read sense amplifier for reading out a data to an outside and an internal verify sense amplifier for reading out a data for an internal operation are provided, separately from each other, to a plurality of banks. Preferably, an internal verify sense amplifier is provided for each prescribed number of memory blocks. There is provided a nonvolatile semiconductor memory device with a background operation function, having a reduced chip occupancy area.

    摘要翻译： 将用于向外部读出数据的外部读取读出放大器和用于读出用于内部操作的数据的内部校验读出放大器彼此分开地提供给多个存储体。 优选地，为每个规定数量的存储块提供内部校验读出放大器。 提供了具有背景操作功能的非易失性半导体存储器件，具有减小的芯片占用面积。

    Electrically erasable and programmable non-volatile memory device and a method of operating the same
    10.
    发明授权
    Electrically erasable and programmable non-volatile memory device and a method of operating the same 失效
    电可擦除和可编程的非易失性存储器件及其操作方法

    公开(公告)号：US5428568A

    公开(公告)日：1995-06-27

    申请号：US933436

    申请日：1992-08-20

    申请人： Shinichi Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya

    发明人： Shinichi Kobayashi ,  Yasushi Terada ,  Takeshi Nakayama ,  Yoshikazu Miyawaki ,  Tomoshi Futatsuya

    IPC分类号： G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C11/34

    CPC分类号： G11C16/3409 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C16/3459

    摘要： In a programming mode of operation of a flash type non-volatile semiconductor memory device, an erase voltage pulse is applied a memory cell to bring the memory cell into an erased state. Then, an after-erase writing operation is executed for a memory cell having a threshold voltage lower than a predetermined threshold voltage under the condition of small change in threshold voltage. Alternatively, an erase voltage pulse is applied only to a memory cell having a threshold voltage greater than a predetermined threshold voltage to carry out erasing. Also, after a memory cell is brought to a depletion state by application of an erase voltage pulse, data writing of "0" and "1" is carried out by injection of electrons into the floating gate. The electron injection rate to the floating gate for writing data "0" is set to be greater than that for writing data "1". The state of storing data "1" corresponds to an erase state. According to this scheme, an excessively erased memory cell does not exist and the distribution range of threshold voltage can be reduced. Furthermore, the reprogramming time period for a memory cell data can be carried out in a short time.

    摘要翻译： 在闪存型非易失性半导体存储器件的编程操作模式中，擦除电压脉冲被施加到存储器单元以使存储单元进入擦除状态。 然后，在阈值电压变化小的条件下，对具有低于预定阈值电压的阈值电压的存储单元执行擦除后写入操作。 或者，擦除电压脉冲仅施加到具有大于预定阈值电压的阈值电压的存储器单元以执行擦除。 此外，在通过施加擦除电压脉冲将存储单元置于耗尽状态之后，通过向浮置栅极注入电子来执行“0”和“1”的数据写入。 写入数据“0”的浮动栅极的电子注入速率被设定为大于写入数据“1”的电子注入速率。 存储数据“1”的状态对应于擦除状态。 根据该方案，不存在过度擦除的存储单元，并且可以减小阈值电压的分布范围。 此外，存储单元数据的重新编程时间段可以在短时间内进行。