公开(公告)号：US5841730A

公开(公告)日：1998-11-24

申请号：US790907

申请日：1997-01-29

申请人： Yasuyuki Kai ,  Katsushi Nagaba ,  Shigeo Ohshima

发明人： Yasuyuki Kai ,  Katsushi Nagaba ,  Shigeo Ohshima

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/1048 ,  G11C7/1078

摘要： A semiconductor memory device capable of shortening data reading time in a first read cycle after the mode has been changed from a write mode to a read mode while maintaining high-speed cycle time when data is written despite simple structure, the semiconductor memory device having a memory cell array having a plurality of dynamic memory cells, to which data can be written, data line pairs to which data read from the memory cells and data which must be written on the memory cells are transferred, a write driver for driving the data line pairs in accordance with write data supplied from outside when data is written to the memory cells and an equalizing circuit for setting the data line pairs to an intermediate potential whenever the data line pairs are operated by the write driver.

摘要翻译： 一种半导体存储器件，其能够在模式已经从写入模式改变为读取模式之后在第一读取周期中缩短数据读取时间，同时在尽可能简单的结构写入数据时保持高速循环时间，半导体存储器件具有 存储单元阵列，具有可以写入数据的多个动态存储器单元，从存储单元读取数据的数据线对和必须写入存储单元的数据被传送到其上，用于驱动数据线的写入驱动器 当数据被写入存储单元时，根据从外部提供的写入数据成对，以及均衡电路，用于每当数据线对由写入驱动器操作时将数据线对设置为中间电位。

公开(公告)号：US06226204B1

公开(公告)日：2001-05-01

申请号：US09141450

申请日：1998-08-27

申请人： Kazuko Inuzuka ,  Katsushi Nagaba ,  Shigeo Ohshima

发明人： Kazuko Inuzuka ,  Katsushi Nagaba ,  Shigeo Ohshima

IPC分类号： G11C1604

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： The data output circuit in a clock synchronous DRAM comprises a first data transfer circuit to which the data read from a memory is input and which transfers the input data to the output side in synchronization with an internal clock, an equalizing circuit to which the output of the first data transfer circuit is input during a read operation by a burst operation and to which high-impedance data is input after the read operation, a second data transfer circuit connected to the equalizing circuit, and an output buffer to which the output of the second data transfer circuit is input. The second data transfer circuit transfers all the data to the output buffer in synchronization with an output clock. This eliminates the dependence of the data access time and data hold time on data item and/or cycle and facilitates the timing control of the output control signal.

摘要翻译： 时钟同步DRAM中的数据输出电路包括第一数据传输电路，从存储器读取的数据被输入到该第一数据传输电路，并且将输入数据与内部时钟同步地传送到输出端;均衡电路， 第一数据传送电路在读操作期间通过脉冲串操作输入，并且在读操作之后输入高阻数据，连接到均衡电路的第二数据传输电路和输出缓冲器 第二数据传输电路被输入。 第二数据传输电路与输出时钟同步地将所有数据传送到输出缓冲器。 这消除了数据访问时间和数据保持时间对数据项和/或周期的依赖性，并且便于输出控制信号的定时控制。

公开(公告)号：US5777946A

公开(公告)日：1998-07-07

申请号：US770404

申请日：1996-12-20

申请人： Kazuko Inuzuka ,  Shigeo Ohshima ,  Katsushi Nagaba

发明人： Kazuko Inuzuka ,  Shigeo Ohshima ,  Katsushi Nagaba

IPC分类号： G11C11/407 ,  G11C8/04 ,  G11C11/408

CPC分类号： G11C8/04

摘要： The present invention provides a semiconductor memory circuit capable of high-speed access to a predetermined column portion by a simplified high-speed addressing circuit. The memory circuit in a DRAM is such that a portion of a column addressing circuit normally comprising a counter constitutes a shift register in a column addressing circuit at a preceding stage of a column address buffer so that a plurality of address signal wrappings are realized for accessing the predetermined column portion.

摘要翻译： 本发明提供一种能够通过简化的高速寻址电路高速访问预定列部分的半导体存储器电路。 DRAM中的存储器电路使得通常包括计数器的列寻址电路的一部分在列地址缓冲器的前级构成列寻址电路中的移位寄存器，从而实现多个地址信号包装以进行访问 预定列部分。

公开(公告)号：US07986557B2

公开(公告)日：2011-07-26

申请号：US12533529

申请日：2009-07-31

申请人： Naoya Tokiwa ,  Shigeo Ohshima

发明人： Naoya Tokiwa ,  Shigeo Ohshima

IPC分类号： G11C16/04 ,  G11C5/14

CPC分类号： G11C16/30 ,  G11C5/143 ,  G11C5/145 ,  G11C8/06 ,  G11C8/10 ,  G11C16/0483

摘要： A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.

摘要翻译： 存储器可以包括字线; 位线 对应于字线和位线之间的交点提供的单元; 感测放大器检测数据; 选择用于读出放大器的特定位线以输出读取数据或接收写入数据的列解码器; 行解码器，被配置为选择某个字线; 电荷泵向读出放大器，列解码器和行解码器供电; 基于选择存储器单元的地址来控制读出放大器，列解码器和行解码器的逻辑电路; 向逻辑电路施加电压的第一电源输入; 以及施加比所述第一电源输入的电压高于所述电荷泵的电压的第二电源输入，以及至少在数据读取时和数据写入时间向所述电荷泵供电。

公开(公告)号：US06768691B2

公开(公告)日：2004-07-27

申请号：US10241908

申请日：2002-09-12

申请人： Noriyasu Kumazaki ,  Keiji Maruyama ,  Shigeo Ohshima

发明人： Noriyasu Kumazaki ,  Keiji Maruyama ,  Shigeo Ohshima

IPC分类号： G11C700

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066

摘要： A semiconductor integrated circuit, comprising: a first output driving part which outputs a data signal in sync with a reference clock signal; a second output driving part which outputs a data strobe signal prescribing a timing of said data signal; and a driving control part which separately controls driving ability of said first and second output driving parts.

摘要翻译： 一种半导体集成电路，包括：第一输出驱动部，其与参考时钟信号同步地输出数据信号; 第二输出驱动部，其输出规定所述数据信号的定时的数据选通信号; 以及分别控制所述第一和第二输出驱动部的驱动能力的驱动控制部。

公开(公告)号：US06483772B2

公开(公告)日：2002-11-19

申请号：US09951230

申请日：2001-09-12

申请人： Susumu Ozawa ,  Shigeo Ohshima ,  Katsumi Abe

发明人： Susumu Ozawa ,  Shigeo Ohshima ,  Katsumi Abe

IPC分类号： G11C800

CPC分类号： G11C7/1087 ,  G11C7/1006 ,  G11C7/1078

摘要： A specifying circuit specifies either the first masking method or the second masking method. A first generation circuit generates a signal corresponding to the first method. A second generation circuit generates a signal corresponding to the second method. A third generation circuit generates a write pulse signal on the basis of the output signal of the first generation circuit in response to the specification of the first masking method made by the specifying circuit and on the basis of the output signal of the second generation circuit in response to the specification of the second masking method made by the specifying circuit.

公开(公告)号：US06426915B2

公开(公告)日：2002-07-30

申请号：US09749008

申请日：2000-12-27

申请人： Shigeo Ohshima ,  Nobuo Watanabe

发明人： Shigeo Ohshima ,  Nobuo Watanabe

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/409

摘要： A row access command and column access command are supplied as one packet to an FCRAM in two successive clock cycles in order to shorten random access time and random cycle time. At this time, definition of the read/write operation is made by use of a first command and a decode address of a memory cell array is fetched in response to the first command. When the decode address of the memory cell array is fetched in response to the first command, command control pins of the conventional SDR/DDR-SDRAM are used as address pins.

摘要翻译： 行访问命令和列访问命令在两个连续的时钟周期中作为一个分组提供给FCRAM，以便缩短随机访问时间和随机周期时间。 此时，通过使用第一命令来进行读/写操作的定义，并且响应于第一命令获取存储单元阵列的解码地址。 当响应于第一命令获取存储单元阵列的解码地址时，常规SDR / DDR-SDRAM的命令控制引脚用作地址引脚。

公开(公告)号：US06198690B1

公开(公告)日：2001-03-06

申请号：US09503000

申请日：2000-02-14

申请人： Koji Kato ,  Masahiro Kamoshida ,  Shigeo Ohshima

发明人： Koji Kato ,  Masahiro Kamoshida ,  Shigeo Ohshima

IPC分类号： G11C800

CPC分类号： G11C7/225 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/135

摘要： A clock control circuit includes a forward pulse delay circuit including a plurality of delay circuits for delaying a forward pulse signal FCL, a backward pulse delay circuit including a plurality of delay circuits for delaying a backward pulse signal RCL, a state-hold section including a plurality of state-hold circuits for controlling the operation of the backward pulse delay circuit in accordance with the transmission condition of the forward pulse signal in the forward pulse delay circuit, and an input stop circuit for stopping inputting a pulse corresponding to an external clock signal to the backward pulse delay circuit during a predetermined period from the time point when the external clock signal begins to be supplied.

摘要翻译： 时钟控制电路包括：正向脉冲延迟电路，包括用于延迟正向脉冲信号FCL的多个延迟电路;包括用于延迟反向脉冲信号RCL的多个延迟电路的反向脉冲延迟电路;状态保持部分，包括： 多个状态保持电路，用于根据正向脉冲延迟电路中的正向脉冲信号的发送条件控制反向脉冲延迟电路的操作;以及输入停止电路，用于停止输入对应于外部时钟信号的脉冲 在从外部时钟信号开始供给的时刻起的规定期间内向后向脉冲延迟电路发送。

公开(公告)号：US6163501A

公开(公告)日：2000-12-19

申请号：US520720

申请日：2000-03-08

申请人： Shigeo Ohshima ,  Susumu Ozawa

发明人： Shigeo Ohshima ,  Susumu Ozawa

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/106 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C2207/107

摘要： A synchronous semiconductor memory device comprises: a memory cell array; a decoder circuit for decoding an address, which is supplied in synchronism with a clock, to select a memory cell of the memory cell array; a plurality of main data line pairs, to which data of the memory cell array are transferred; a plurality of data line buffers, each of which is provided in a corresponding one of the main data line pairs and each of which includes a latch circuit; and a plurality of peripheral data lines for transferring data of each of the data line buffers to a data input/output terminal, wherein a plurality of bits of data per data input/output terminal read out of the memory cell array are transferred to the data line buffers via the main data line pairs in parallel, and while head data of the plurality of bits of data pass through the latch circuits to be transferred to one of the peripheral data lines, a plurality of continuous data are temporarily held by the latch circuit, and subsequent data are sequentially transferred to the same peripheral data line as the one of the peripheral data lines, to which the head data have been transferred. Thus, it is possible to decrease the number of peripheral data lines to reduce the chip size of an SDRAM while adopting a pre-fetch system for accelerating a data transfer cycle.

摘要翻译： 同步半导体存储器件包括：存储单元阵列; 解码器电路，用于对与时钟同步地提供的地址进行解码，以选择存储单元阵列的存储单元; 传送存储单元阵列的数据的多个主数据线对; 多个数据线缓冲器，每个数据线缓冲器被提供在相应的一个主数据线对中，并且每个数据线缓冲器包括一个锁存电路; 以及用于将每个数据线缓冲器的数据传送到数据输入/输出端子的多个外围数据线，其中从存储单元阵列读出的每个数据输入/输出端子的多个数据位被传送到数据 并行地经由主数据线对的行缓冲器，并且当多个数据位的头数据通过锁存电路以传送到外围数据线之一时，多个连续数据被锁存电路暂时保持 并且随后的数据被顺序传送到与传送头数据的外围数据线之一相同的外围数据线。 因此，可以减少外围数据线的数量，以减少SDRAM的芯片尺寸，同时采用用于加速数据传输周期的预取系统。

公开(公告)号：US5051954A

公开(公告)日：1991-09-24

申请号：US406420

申请日：1989-09-11

申请人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/10

CPC分类号： G11C11/4097 ,  G11C11/408 ,  G11C11/4096

摘要： Memory cells disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by a first gate. One memory cell column in the n memory cell colunns in a selected block is selected by a second gate. One memory cell in a selected memory cell column is selected by a row address. The data in a selected memory cell are stored in a register and output therefrom.