公开(公告)号：US06483772B2

公开(公告)日：2002-11-19

申请号：US09951230

申请日：2001-09-12

申请人： Susumu Ozawa ,  Shigeo Ohshima ,  Katsumi Abe

发明人： Susumu Ozawa ,  Shigeo Ohshima ,  Katsumi Abe

IPC分类号： G11C800

CPC分类号： G11C7/1087 ,  G11C7/1006 ,  G11C7/1078

摘要： A specifying circuit specifies either the first masking method or the second masking method. A first generation circuit generates a signal corresponding to the first method. A second generation circuit generates a signal corresponding to the second method. A third generation circuit generates a write pulse signal on the basis of the output signal of the first generation circuit in response to the specification of the first masking method made by the specifying circuit and on the basis of the output signal of the second generation circuit in response to the specification of the second masking method made by the specifying circuit.

公开(公告)号：US6163501A

公开(公告)日：2000-12-19

申请号：US520720

申请日：2000-03-08

申请人： Shigeo Ohshima ,  Susumu Ozawa

发明人： Shigeo Ohshima ,  Susumu Ozawa

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C7/106 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C2207/107

摘要： A synchronous semiconductor memory device comprises: a memory cell array; a decoder circuit for decoding an address, which is supplied in synchronism with a clock, to select a memory cell of the memory cell array; a plurality of main data line pairs, to which data of the memory cell array are transferred; a plurality of data line buffers, each of which is provided in a corresponding one of the main data line pairs and each of which includes a latch circuit; and a plurality of peripheral data lines for transferring data of each of the data line buffers to a data input/output terminal, wherein a plurality of bits of data per data input/output terminal read out of the memory cell array are transferred to the data line buffers via the main data line pairs in parallel, and while head data of the plurality of bits of data pass through the latch circuits to be transferred to one of the peripheral data lines, a plurality of continuous data are temporarily held by the latch circuit, and subsequent data are sequentially transferred to the same peripheral data line as the one of the peripheral data lines, to which the head data have been transferred. Thus, it is possible to decrease the number of peripheral data lines to reduce the chip size of an SDRAM while adopting a pre-fetch system for accelerating a data transfer cycle.

摘要翻译： 同步半导体存储器件包括：存储单元阵列; 解码器电路，用于对与时钟同步地提供的地址进行解码，以选择存储单元阵列的存储单元; 传送存储单元阵列的数据的多个主数据线对; 多个数据线缓冲器，每个数据线缓冲器被提供在相应的一个主数据线对中，并且每个数据线缓冲器包括一个锁存电路; 以及用于将每个数据线缓冲器的数据传送到数据输入/输出端子的多个外围数据线，其中从存储单元阵列读出的每个数据输入/输出端子的多个数据位被传送到数据 并行地经由主数据线对的行缓冲器，并且当多个数据位的头数据通过锁存电路以传送到外围数据线之一时，多个连续数据被锁存电路暂时保持 并且随后的数据被顺序传送到与传送头数据的外围数据线之一相同的外围数据线。 因此，可以减少外围数据线的数量，以减少SDRAM的芯片尺寸，同时采用用于加速数据传输周期的预取系统。

公开(公告)号：US07986557B2

公开(公告)日：2011-07-26

申请号：US12533529

申请日：2009-07-31

申请人： Naoya Tokiwa ,  Shigeo Ohshima

发明人： Naoya Tokiwa ,  Shigeo Ohshima

IPC分类号： G11C16/04 ,  G11C5/14

CPC分类号： G11C16/30 ,  G11C5/143 ,  G11C5/145 ,  G11C8/06 ,  G11C8/10 ,  G11C16/0483

摘要： A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.

摘要翻译： 存储器可以包括字线; 位线 对应于字线和位线之间的交点提供的单元; 感测放大器检测数据; 选择用于读出放大器的特定位线以输出读取数据或接收写入数据的列解码器; 行解码器，被配置为选择某个字线; 电荷泵向读出放大器，列解码器和行解码器供电; 基于选择存储器单元的地址来控制读出放大器，列解码器和行解码器的逻辑电路; 向逻辑电路施加电压的第一电源输入; 以及施加比所述第一电源输入的电压高于所述电荷泵的电压的第二电源输入，以及至少在数据读取时和数据写入时间向所述电荷泵供电。

公开(公告)号：US06768691B2

公开(公告)日：2004-07-27

申请号：US10241908

申请日：2002-09-12

申请人： Noriyasu Kumazaki ,  Keiji Maruyama ,  Shigeo Ohshima

发明人： Noriyasu Kumazaki ,  Keiji Maruyama ,  Shigeo Ohshima

IPC分类号： G11C700

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066

摘要： A semiconductor integrated circuit, comprising: a first output driving part which outputs a data signal in sync with a reference clock signal; a second output driving part which outputs a data strobe signal prescribing a timing of said data signal; and a driving control part which separately controls driving ability of said first and second output driving parts.

摘要翻译： 一种半导体集成电路，包括：第一输出驱动部，其与参考时钟信号同步地输出数据信号; 第二输出驱动部，其输出规定所述数据信号的定时的数据选通信号; 以及分别控制所述第一和第二输出驱动部的驱动能力的驱动控制部。

公开(公告)号：US06426915B2

公开(公告)日：2002-07-30

申请号：US09749008

申请日：2000-12-27

申请人： Shigeo Ohshima ,  Nobuo Watanabe

发明人： Shigeo Ohshima ,  Nobuo Watanabe

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/409

摘要： A row access command and column access command are supplied as one packet to an FCRAM in two successive clock cycles in order to shorten random access time and random cycle time. At this time, definition of the read/write operation is made by use of a first command and a decode address of a memory cell array is fetched in response to the first command. When the decode address of the memory cell array is fetched in response to the first command, command control pins of the conventional SDR/DDR-SDRAM are used as address pins.

摘要翻译： 行访问命令和列访问命令在两个连续的时钟周期中作为一个分组提供给FCRAM，以便缩短随机访问时间和随机周期时间。 此时，通过使用第一命令来进行读/写操作的定义，并且响应于第一命令获取存储单元阵列的解码地址。 当响应于第一命令获取存储单元阵列的解码地址时，常规SDR / DDR-SDRAM的命令控制引脚用作地址引脚。

公开(公告)号：US06198690B1

公开(公告)日：2001-03-06

申请号：US09503000

申请日：2000-02-14

申请人： Koji Kato ,  Masahiro Kamoshida ,  Shigeo Ohshima

发明人： Koji Kato ,  Masahiro Kamoshida ,  Shigeo Ohshima

IPC分类号： G11C800

CPC分类号： G11C7/225 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/135

摘要： A clock control circuit includes a forward pulse delay circuit including a plurality of delay circuits for delaying a forward pulse signal FCL, a backward pulse delay circuit including a plurality of delay circuits for delaying a backward pulse signal RCL, a state-hold section including a plurality of state-hold circuits for controlling the operation of the backward pulse delay circuit in accordance with the transmission condition of the forward pulse signal in the forward pulse delay circuit, and an input stop circuit for stopping inputting a pulse corresponding to an external clock signal to the backward pulse delay circuit during a predetermined period from the time point when the external clock signal begins to be supplied.

摘要翻译： 时钟控制电路包括：正向脉冲延迟电路，包括用于延迟正向脉冲信号FCL的多个延迟电路;包括用于延迟反向脉冲信号RCL的多个延迟电路的反向脉冲延迟电路;状态保持部分，包括： 多个状态保持电路，用于根据正向脉冲延迟电路中的正向脉冲信号的发送条件控制反向脉冲延迟电路的操作;以及输入停止电路，用于停止输入对应于外部时钟信号的脉冲 在从外部时钟信号开始供给的时刻起的规定期间内向后向脉冲延迟电路发送。

公开(公告)号：US5051954A

公开(公告)日：1991-09-24

申请号：US406420

申请日：1989-09-11

申请人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/10

CPC分类号： G11C11/4097 ,  G11C11/408 ,  G11C11/4096

摘要： Memory cells disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by a first gate. One memory cell column in the n memory cell colunns in a selected block is selected by a second gate. One memory cell in a selected memory cell column is selected by a row address. The data in a selected memory cell are stored in a register and output therefrom.

公开(公告)号：US4883978A

公开(公告)日：1989-11-28

申请号：US167082

申请日：1988-03-11

申请人： Shigeo Ohshima ,  Hiroshi Sahara

发明人： Shigeo Ohshima ,  Hiroshi Sahara

IPC分类号： H03K19/00 ,  G11C11/401 ,  G11C11/409 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

CPC分类号： H03K17/162 ,  H03K19/00361

摘要： For a semiconductor integrated circuit having a data output buffer, separate power source pads and separate reference pads are provided for the data output buffer and the circuit components. Thus, any potential fluctuations or noise generated in the data output buffer are not transmitted to the circuit components, resulting in decreased circuit malfunction.

公开(公告)号：US08000155B2

公开(公告)日：2011-08-16

申请号：US13005582

申请日：2011-01-13

申请人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

发明人： Toshiaki Edahiro ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

IPC分类号： G11C7/22 ,  G11C7/06 ,  G11C11/00 ,  G11C17/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/72

摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

公开(公告)号：US07800967B2

公开(公告)日：2010-09-21

申请号：US12324953

申请日：2008-11-28

申请人： Satoru Takase ,  Shigeo Ohshima

发明人： Satoru Takase ,  Shigeo Ohshima

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C7/06 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

摘要： This disclosure concerns a memory including: word lines extending to a first direction; bit lines extending to a second direction crossing the first direction; a memory cell array including cell blocks each including memory cells respectively provided corresponding to intersection points of the word lines and the bit lines; and sense amplifiers provided corresponding to the bit lines, wherein the sense amplifiers copies existing data stored in a first cell block within the memory cell array to a plurality of memory cells, the memory cells being included in second and third cell blocks different from the first cell block, and alternately arranged in an extension direction of the word lines and also alternately arranged in an extension direction of the bit lines, and the sense amplifiers reads data from the second cell block or the third cell block, at a time of outputting data to outside of the sense amplifiers.

摘要翻译： 本公开涉及一种存储器，包括：延伸到第一方向的字线; 位线延伸到与第一方向交叉的第二方向; 包括单元块的存储单元阵列，每个单元块包括分别对应于字线和位线的交点提供的存储单元; 以及对应于所述位线的感测放大器，其中所述感测放大器将存储在所述存储单元阵列内的第一单元块中的现有数据复制到多个存储器单元，所述存储单元包括在与所述第一和第三单元块不同的第二和第三单元块中 并且在字线的延伸方向上交替布置，并且还在位线的延伸方向上交替布置，并且读出放大器在输出数据时从第二单元块或第三单元块读取数据 到感应放大器外面。