公开(公告)号：US06713341B2

公开(公告)日：2004-03-30

申请号：US10162156

申请日：2002-06-03

申请人： Yi-Nan Chen ,  Hsien-Wen Liu ,  Hsin-Chuan Tsai

发明人： Yi-Nan Chen ,  Hsien-Wen Liu ,  Hsin-Chuan Tsai

IPC分类号： H01L218242

CPC分类号： H01L29/66181

摘要： A method of forming a bottle-shaped trench in a semiconductor substrate. The method is suitable for formation of the capacitor of DRAM. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. A nitride film is then formed on the top portion of the trench. Next, the semiconductor substrate is etched through the bottom portion of the trench by a solution of hydrogen peroxide and hydrofluoric acid as the etchant to form a bottle-shaped trench followed by removal of the nitride film.

摘要翻译： 一种在半导体衬底中形成瓶形沟槽的方法。 该方法适用于DRAM的电容器的形成。 首先，选择性地蚀刻半导体衬底以形成沟槽，其中沟槽具有顶部和底部。 然后在沟槽的顶部上形成氮化物膜。 接下来，通过作为蚀刻剂的过氧化氢和氢氟酸的溶液，通过沟槽的底部蚀刻半导体衬底，以形成瓶状沟槽，随后除去氮化物膜。

公开(公告)号：US06211006B1

公开(公告)日：2001-04-03

申请号：US09435031

申请日：1999-11-05

申请人： Hsin-Chuan Tsai ,  Yi-Nan Chen ,  Pei-Ing Paul Lee

发明人： Hsin-Chuan Tsai ,  Yi-Nan Chen ,  Pei-Ing Paul Lee

IPC分类号： H01L218242

CPC分类号： H01L27/1087

摘要： The present invention relates to a method of forming a trench-type capacitor. More particularly, the plate areas of the trench-type capacitor are increased according to the present invention. The method of this invention comprises the steps of: providing a semiconductor substrate; forming a first trench in the semiconductor substrate, wherein the first trench has a first predetermined depth in the semiconductor substrate; forming first spacers on the side-walls of the first trench, wherein the first spacers include second spacers formed at the bottom of the first trench and third spacers exposed to the air; forming a second trench by aligning the semiconductor substrate with masks of the first spacers and etching the semiconductor substrate to a second predetermined depth; forming a first conducting layer by doping ions into the semiconductor substrate in the second trench; forming an oxide layer on the surface of the first conducting layer by oxidation, wherein the thickness of the oxide layer is less than that of the first conducting layer; forming a second conducting layer by removing the oxide layer, removing the first spacers; forming a dielectric layer upon the second conducting layer; and forming a third conducting layer upon the dielectric layer.

摘要翻译： 本发明涉及一种形成沟槽型电容器的方法。 更具体地，根据本发明，沟槽型电容器的板区域增加。 本发明的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底中形成第一沟槽，其中所述第一沟槽在所述半导体衬底中具有第一预定深度; 在所述第一沟槽的侧壁上形成第一间隔物，其中所述第一间隔物包括形成在所述第一沟槽的底部的第二间隔物和暴露于空气的第三间隔物; 通过将半导体衬底与第一间隔物的掩模对准并将半导体衬底蚀刻到第二预定深度来形成第二沟槽; 通过在第二沟槽中将离子掺杂到半导体衬底中形成第一导电层; 通过氧化在所述第一导电层的表面上形成氧化物层，其中所述氧化物层的厚度小于所述第一导电层的厚度; 通过去除所述氧化物层来形成第二导电层，去除所述第一间隔物; 在所述第二导电层上形成电介质层; 以及在所述电介质层上形成第三导电层。

公开(公告)号：US06929998B2

公开(公告)日：2005-08-16

申请号：US10628894

申请日：2003-07-28

申请人： Yi-Nan Chen ,  Hsin-Chuan Tsai

发明人： Yi-Nan Chen ,  Hsin-Chuan Tsai

IPC分类号： H01L21/3065 ,  H01L21/311 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242

CPC分类号： H01L29/66181 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31658 ,  H01L27/1087

摘要： A method for forming a bottle-shaped trench. A conductive layer surrounded by a doped layer is filled in a lower portion of a trench formed in a substrate. A doping region is formed in the substrate around the doped layer by a heat treatment. A collar silicon nitride layer is formed over an upper portion of the sidewall of the trench. The conductive layer and the doped layer are successively removed using the collar silicon nitride layer as a mask. The doping region is partially oxidized to form a doped oxide region thereon. The doped oxide region is removed to form a bottle-shaped trench. A conformable rugged polysilicon layer is formed in the lower portion of the bottle-shaped trench.

摘要翻译： 一种用于形成瓶形沟槽的方法。 由掺杂层围绕的导电层填充在形成在衬底中的沟槽的下部。 通过热处理在掺杂层周围的衬底中形成掺杂区域。 环状氮化硅层形成在沟槽的侧壁的上部上。 使用环状氮化硅层作为掩模，依次去除导电层和掺杂层。 掺杂区域被部分氧化以在其上形成掺杂的氧化物区域。 去除掺杂的氧化物区域以形成瓶状沟槽。 在瓶状沟槽的下部形成一个坚固耐用的多晶硅层。

公开(公告)号：US06365506B1

公开(公告)日：2002-04-02

申请号：US09859762

申请日：2001-05-17

申请人： Chih-Han Chang ,  Hsin-Chuan Tsai

发明人： Chih-Han Chang ,  Hsin-Chuan Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L21/7682

摘要： This invention relates to a dual damascene process with porous low-k dielectric material. A first insulating layer is formed on a porous low-k dielectric layer. The first insulating layer has a first pattern for defining a first opening in the low-k dielectric layer. Also, the invention includes the step of forming a second insulating layer on the first insulating layer. Both the first insulating layer and the second insulating layer are used as a hard mask, the two insulating layers being of different materials. The second insulating layer has a second pattern for defining a second opening in the low-k dielectric layer. Then, at least one etch is performed to form a dual damascene structure in the porous low-k dielectric layer by the different insulating layers which cause different protection time in etching the porous low-k dielectric layer.

摘要翻译： 本发明涉及具有多孔低k电介质材料的双镶嵌工艺。 在多孔低k电介质层上形成第一绝缘层。 第一绝缘层具有用于限定低k电介质层中的第一开口的第一图案。 此外，本发明包括在第一绝缘层上形成第二绝缘层的步骤。 第一绝缘层和第二绝缘层都用作硬掩模，两个绝缘层是不同的材料。 第二绝缘层具有用于限定低k电介质层中的第二开口的第二图案。 然后，通过不同的绝缘层在多孔低k电介质层中进行至少一次蚀刻以形成多孔低k电介质层中的双镶嵌结构，这在蚀刻多孔低k电介质层时引起不同的保护时间。

公开(公告)号：US06834547B2

公开(公告)日：2004-12-28

申请号：US10440934

申请日：2003-05-19

申请人： Chih-Kun Chen ,  Yao-Hsiung Kung ,  Chung-Min Lin ,  Hsin-Chuan Tsai

发明人： Chih-Kun Chen ,  Yao-Hsiung Kung ,  Chung-Min Lin ,  Hsin-Chuan Tsai

IPC分类号： G01N100

CPC分类号： G01N27/121

摘要： A humidity sensor and fabrication method thereof. In the humidity sensor of the present invention, two comb-type electrodes with a plurality of teeth are disposed on a semiconductor substrate. A SiO2 sensing film is disposed between the teeth of the two comb-type electrodes on the substrate. A predetermined voltage is applied between the two comb-type electrodes, a leakage current between the two electrodes is detected, and the humidity in the environment is measured according thereto.

公开(公告)号：US6117726A

公开(公告)日：2000-09-12

申请号：US326668

申请日：1999-06-07

申请人： Hsin-Chuan Tsai ,  Pei-Ing Paul Lee

发明人： Hsin-Chuan Tsai ,  Pei-Ing Paul Lee

IPC分类号： H01L21/8242

CPC分类号： H01L27/10867

摘要： A method of making a trench capacitor including the following steps: forming a first trench of predetermined depth into a semiconductor substrate; forming an electrode plate on the side-wall of a bottom of the first trench; forming a dielectric layer on the electrode plate; forming a first conductive portion on the dielectric layer, wherein the first conductive portion fills the bottom of the first trench to form a second trench; forming an insulation layer to fill the bottom portion of the second trench to make a third trench in the second trench; forming a conductive spacer along the side-wall of the third trench; etching the insulation layer using the conductive spacer as a mask to form a forth trench; and then filling the forth trench with a conductive material.

摘要翻译： 一种制造沟槽电容器的方法，包括以下步骤：将预定深度的第一沟槽形成为半导体衬底; 在所述第一沟槽的底部的侧壁上形成电极板; 在所述电极板上形成电介质层; 在所述电介质层上形成第一导电部分，其中所述第一导电部分填充所述第一沟槽的底部以形成第二沟槽; 形成绝缘层以填充所述第二沟槽的底部以在所述第二沟槽中形成第三沟槽; 沿着所述第三沟槽的侧壁形成导电间隔物; 使用导电间隔物作为掩模蚀刻绝缘层以形成第四沟槽; 然后用导电材料填充第四沟槽。

公开(公告)号：US06448150B1

公开(公告)日：2002-09-10

申请号：US09055254

申请日：1998-04-06

申请人： Hsin-Chuan Tsai ,  Pei-Ing Lee

发明人： Hsin-Chuan Tsai ,  Pei-Ing Lee

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  H01L21/31055

摘要： A method for forming shallow trench isolation in an integrated circuit is introduced. Firstly, the first silicon oxide layer and a silicon nitride layer are formed subsequently on the silicon substrate. Then lithography and etching are used to open a shallow trench. Then thermal oxidation is performed. The following step is to form the shallow trench isolation by forming the second silicon oxide with high density plasma enhanced chemical vapor deposition. Then an organic spin-on-glass is coated and low temperature baking is performed. After that, partial etching back is performed to remove spin-on-glass outside the shallow trench. This etching recipe has high selectivity between the second silicon oxide layer to spin-on-glass. Then curing at temperature above 800° C. and etching back are performed with silicon nitride as end point.

摘要翻译： 介绍了一种在集成电路中形成浅沟槽隔离的方法。 首先，在硅衬底上随后形成第一氧化硅层和氮化硅层。 然后使用光刻和蚀刻来打开浅沟槽。 然后进行热氧化。 以下步骤是通过用高密度等离子体增强化学气相沉积形成第二氧化硅来形成浅沟槽隔离。 然后涂覆有机旋涂玻璃并进行低温烘烤。 之后，进行部分蚀刻以去除浅沟槽外的旋涂玻璃。 该蚀刻配方在第二氧化硅层与旋涂玻璃之间具有高选择性。 然后在高于800℃的温度下固化，并且用氮化硅作为终点进行蚀刻。

公开(公告)号：US6093601A

公开(公告)日：2000-07-25

申请号：US167491

申请日：1998-10-07

申请人： Hsin-Chuan Tsai ,  Yinan Chen

发明人： Hsin-Chuan Tsai ,  Yinan Chen

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/20 ,  H01L21/8234

CPC分类号： H01L28/87

摘要： A method of fabricating a stack crown capacitor of a dynamic random access memory (DRAM) cell by using an oxynitride mask is disclosed. First, a dielectric layer and a silicon nitride layer are sequentially deposited over a substrate with an electrical device. Next, forming a contact in the silicon nitride layer and the dielectric layer, and depositing a first polysilicon layer to fill the contact. Next, depositing an oxide layer and an oxynitride layer sequentially, and then defining a bottom electrode pattern for etching the oxynitride layer and the oxide layer. Then, laterally etching the oxide layer, and depositing a second polysilicon layer. Next, etching the second polysilicon layer and the first polysilicon layer by using the oxynitride layer as a mask to form the bottom electrode. Next, removing the oxynitride layer, the oxide layer and partial silicon nitride layer. Finally, forming an interelectrode dielectric layer and a top electrode.

摘要翻译： 公开了一种通过使用氧氮化物掩模制造动态随机存取存储器（DRAM）单元的堆叠冠电容器的方法。 首先，电介质层和氮化硅层依次沉积在具有电子器件的衬底上。 接下来，在氮化硅层和电介质层中形成接触，并沉积第一多晶硅层以填充接触。 接下来，依次沉积氧化物层和氧氮化物层，然后限定用于蚀刻氧氮化物层和氧化物层的底部电极图案。 然后，横向蚀刻氧化物层，并沉积第二多晶硅层。 接下来，通过使用氧氮化物层作为掩模来蚀刻第二多晶硅层和第一多晶硅层以形成底部电极。 接下来，除去氧氮化物层，氧化物层和部分氮化硅层。 最后，形成电极间电介质层和顶电极。

公开(公告)号：US6025263A

公开(公告)日：2000-02-15

申请号：US927287

申请日：1997-09-11

申请人： Hsin-Chuan Tsai ,  Chung-Min Lin

发明人： Hsin-Chuan Tsai ,  Chung-Min Lin

IPC分类号： H01L21/316 ,  H01L21/4763

CPC分类号： H01L21/02164 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31612 ,  Y10S438/958

摘要： A underlayer process for high O.sub.3 /TEOS interlayer dielectric deposition is disclosed. First, a layer of metal pattern is defined on a semiconductor substrate, then a layer of dielectric underlayer is deposited, next, a high O.sub.3 /TEOS interlayer dielectric is formed to achieve planarization. The key point of this process is to apply materials with higher refraction index than conventional PE-TEOS for forming interlayer dielectric underlayer. The mentioned material can be PE-SiH.sub.4 with a constant or decreasing refraction index with the distance from the semiconductor substrate. The underlayer can also be bi-layer structure consisting of high refraction index bottom layer and low refraction index surface layer. This invention can effectively suppress the problem caused from high surface sensitivity of O.sub.3 /TEOS, and improve the quality of interlayer dielectric planarization process dramatically.

摘要翻译： 公开了一种用于高O 3 / TEOS层间电介质沉积的底层工艺。 首先，在半导体衬底上限定一层金属图案，然后沉积一层电介质底层，接着形成高O 3 / TEOS层间电介质以实现平坦化。 该方法的关键在于应用具有比常规PE-TEOS更高的折射率的材料以形成层间电介质底层。 所提到的材料可以是具有恒定或降低折射率的距离与半导体衬底的距离的PE-SiH4。 底层也可以是由高折射率底层和低折射率表面层组成的双层结构。 本发明可以有效地抑制由O3 / TEOS的高表面灵敏度引起的问题，并显着提高层间介质平坦化工艺的质量。

公开(公告)号：US06761624B2

公开(公告)日：2004-07-13

申请号：US10053161

申请日：2002-01-15

申请人： Shan-Chang Wang ,  Hsin-Chuan Tsai

发明人： Shan-Chang Wang ,  Hsin-Chuan Tsai

IPC分类号： B24B4106

CPC分类号： B24B37/345

摘要： A chemical mechanical polish apparatus comprises a platen having a polishing pad thereon, a wafer carrier holding a wafer on the polishing pad, and a pusher. The pusher has a base disk and at least two guiding structures at the rim of the base disk. Each guiding structure has a shell with an opening, an elastic device and a pin moving through the opening, wherein the opening is non-linear.

摘要翻译： 化学机械抛光装置包括其上具有抛光垫的压板，在抛光垫上保持晶片的晶片载体和推动器。 推动器具有基盘和在基盘的边缘处的至少两个引导结构。 每个引导结构具有开口的外壳，弹性装置和穿过开口的销，其中开口是非线性的。