公开(公告)号：US06713341B2

公开(公告)日：2004-03-30

申请号：US10162156

申请日：2002-06-03

申请人： Yi-Nan Chen ,  Hsien-Wen Liu ,  Hsin-Chuan Tsai

发明人： Yi-Nan Chen ,  Hsien-Wen Liu ,  Hsin-Chuan Tsai

IPC分类号： H01L218242

CPC分类号： H01L29/66181

摘要： A method of forming a bottle-shaped trench in a semiconductor substrate. The method is suitable for formation of the capacitor of DRAM. First, the semiconductor substrate is selectively etched to form a trench, wherein the trench has a top portion and a bottom portion. A nitride film is then formed on the top portion of the trench. Next, the semiconductor substrate is etched through the bottom portion of the trench by a solution of hydrogen peroxide and hydrofluoric acid as the etchant to form a bottle-shaped trench followed by removal of the nitride film.

摘要翻译： 一种在半导体衬底中形成瓶形沟槽的方法。 该方法适用于DRAM的电容器的形成。 首先，选择性地蚀刻半导体衬底以形成沟槽，其中沟槽具有顶部和底部。 然后在沟槽的顶部上形成氮化物膜。 接下来，通过作为蚀刻剂的过氧化氢和氢氟酸的溶液，通过沟槽的底部蚀刻半导体衬底，以形成瓶状沟槽，随后除去氮化物膜。

公开(公告)号：US06929998B2

公开(公告)日：2005-08-16

申请号：US10628894

申请日：2003-07-28

申请人： Yi-Nan Chen ,  Hsin-Chuan Tsai

发明人： Yi-Nan Chen ,  Hsin-Chuan Tsai

IPC分类号： H01L21/3065 ,  H01L21/311 ,  H01L21/316 ,  H01L21/334 ,  H01L21/8242

CPC分类号： H01L29/66181 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31658 ,  H01L27/1087

摘要： A method for forming a bottle-shaped trench. A conductive layer surrounded by a doped layer is filled in a lower portion of a trench formed in a substrate. A doping region is formed in the substrate around the doped layer by a heat treatment. A collar silicon nitride layer is formed over an upper portion of the sidewall of the trench. The conductive layer and the doped layer are successively removed using the collar silicon nitride layer as a mask. The doping region is partially oxidized to form a doped oxide region thereon. The doped oxide region is removed to form a bottle-shaped trench. A conformable rugged polysilicon layer is formed in the lower portion of the bottle-shaped trench.

摘要翻译： 一种用于形成瓶形沟槽的方法。 由掺杂层围绕的导电层填充在形成在衬底中的沟槽的下部。 通过热处理在掺杂层周围的衬底中形成掺杂区域。 环状氮化硅层形成在沟槽的侧壁的上部上。 使用环状氮化硅层作为掩模，依次去除导电层和掺杂层。 掺杂区域被部分氧化以在其上形成掺杂的氧化物区域。 去除掺杂的氧化物区域以形成瓶状沟槽。 在瓶状沟槽的下部形成一个坚固耐用的多晶硅层。

公开(公告)号：US06211006B1

公开(公告)日：2001-04-03

申请号：US09435031

申请日：1999-11-05

申请人： Hsin-Chuan Tsai ,  Yi-Nan Chen ,  Pei-Ing Paul Lee

发明人： Hsin-Chuan Tsai ,  Yi-Nan Chen ,  Pei-Ing Paul Lee

IPC分类号： H01L218242

CPC分类号： H01L27/1087

摘要： The present invention relates to a method of forming a trench-type capacitor. More particularly, the plate areas of the trench-type capacitor are increased according to the present invention. The method of this invention comprises the steps of: providing a semiconductor substrate; forming a first trench in the semiconductor substrate, wherein the first trench has a first predetermined depth in the semiconductor substrate; forming first spacers on the side-walls of the first trench, wherein the first spacers include second spacers formed at the bottom of the first trench and third spacers exposed to the air; forming a second trench by aligning the semiconductor substrate with masks of the first spacers and etching the semiconductor substrate to a second predetermined depth; forming a first conducting layer by doping ions into the semiconductor substrate in the second trench; forming an oxide layer on the surface of the first conducting layer by oxidation, wherein the thickness of the oxide layer is less than that of the first conducting layer; forming a second conducting layer by removing the oxide layer, removing the first spacers; forming a dielectric layer upon the second conducting layer; and forming a third conducting layer upon the dielectric layer.

摘要翻译： 本发明涉及一种形成沟槽型电容器的方法。 更具体地，根据本发明，沟槽型电容器的板区域增加。 本发明的方法包括以下步骤：提供半导体衬底; 在所述半导体衬底中形成第一沟槽，其中所述第一沟槽在所述半导体衬底中具有第一预定深度; 在所述第一沟槽的侧壁上形成第一间隔物，其中所述第一间隔物包括形成在所述第一沟槽的底部的第二间隔物和暴露于空气的第三间隔物; 通过将半导体衬底与第一间隔物的掩模对准并将半导体衬底蚀刻到第二预定深度来形成第二沟槽; 通过在第二沟槽中将离子掺杂到半导体衬底中形成第一导电层; 通过氧化在所述第一导电层的表面上形成氧化物层，其中所述氧化物层的厚度小于所述第一导电层的厚度; 通过去除所述氧化物层来形成第二导电层，去除所述第一间隔物; 在所述第二导电层上形成电介质层; 以及在所述电介质层上形成第三导电层。

公开(公告)号：US08963282B2

公开(公告)日：2015-02-24

申请号：US13231961

申请日：2011-09-14

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/72 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC分类号： H01L23/562 ,  H01L21/311 ,  H01L21/561 ,  H01L21/76224 ,  H01L21/78 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

摘要翻译： 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US08692245B2

公开(公告)日：2014-04-08

申请号：US13214227

申请日：2011-08-21

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L23/544 ,  H01L23/482 ,  H01L21/762

CPC分类号： H01L21/76224 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.

摘要翻译： 本发明在第一方面提出了一种具有裂纹停止结构的半导体结构。 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。

公开(公告)号：US08642479B2

公开(公告)日：2014-02-04

申请号：US13183358

申请日：2011-07-14

申请人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/31144 ,  H01L21/32137

摘要： A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

摘要翻译： 提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上 垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。

公开(公告)号：US08551881B2

公开(公告)日：2013-10-08

申请号：US13093735

申请日：2011-04-25

申请人： Shing-Yih Shih ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Shing-Yih Shih ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/44

CPC分类号： H01L21/304 ,  H01L21/76898

摘要： A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias.

摘要翻译： 公开了一种斜面修整三维（3D）半导体器件的方法，包括提供衬底上的堆叠层，并通过其中的衬底通孔（TSV），其中衬底的边缘是弯曲的，对弯曲的 边缘，用于获得平面边缘，并且使基板变薄以暴露通过的基板通孔。

公开(公告)号：US08487397B2

公开(公告)日：2013-07-16

申请号：US13093742

申请日：2011-04-25

申请人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.

摘要翻译： 具有自对准接触的集成电路包括其上形成有晶体管的衬底，介电间隔物，保护屏障和导电层。 晶体管包括掩模层和形成在掩模层的相对侧上的一对绝缘间隔物。 电介质间隔物部分地覆盖晶体管的至少一个绝缘间隔物。 保护屏障形成在电介质间隔物上。 导电层形成在掩模层，保护屏障，电介质间隔物，绝缘间隔物和介电间隔物上，作为用于接触晶体管的源/漏区的自对准接触。

公开(公告)号：US20130099309A1

公开(公告)日：2013-04-25

申请号：US13281293

申请日：2011-10-25

申请人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/823487 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.

摘要翻译： 公开了一种垂直MOSFET静电放电装置，包括：包括多个沟槽的衬底;设置在每个沟槽中的凹入栅极，设置在两个相邻凹入栅极中的每一个之间的漏极区域，设置在每个漏极区域下方的静电放电注入区域， 以及围绕并设置在凹入栅极和静电放电注入区域下面的源极区域。

公开(公告)号：US08415729B2

公开(公告)日：2013-04-09

申请号：US13081500

申请日：2011-04-07

申请人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L27/108

CPC分类号： H01L29/7397 ,  H01L29/4236 ,  H01L29/66348

摘要： A power device with trenched gate structure, includes: a substrate having a first face and a second face opposing to the first face, a body region of a first conductivity type disposed in the substrate, a base region of a second conductivity type disposed in the body region, a cathode region of the first conductivity type disposed in the base region, an anode region of the second conductivity type disposed in the substrate at the second face a trench disposed in the substrate and extending from the first face into the body region, and the cathode region encompassing the trench, wherein the trench has a wavelike sidewall, a gate structure disposed in the trench and an accumulation region disposed in the body region and along the wavelike sidewall. The wavelike sidewall can increase the base current of the bipolar transistor and increase the performance of the IGBT.

摘要翻译： 具有沟槽栅极结构的功率器件包括：具有第一面和与第一面相对的第二面的衬底，设置在衬底中的第一导电类型的主体区域，设置在第二导电类型的基极区域 设置在所述基底区域中的所述第一导电类型的阴极区域，所述第二导电类型的阳极区域设置在所述基板的所述第二面处，所述沟槽设置在所述基板中并且从所述第一面延伸到所述主体区域中， 以及包围所述沟槽的阴极区域，其中所述沟槽具有波状侧壁，设置在所述沟槽中的栅极结构以及设置在所述体区中并沿着所述波浪形侧壁的堆积区域。 波浪形侧壁可以增加双极晶体管的基极电流并增加IGBT的性能。