公开(公告)号：US20050138340A1

公开(公告)日：2005-06-23

申请号：US10744186

申请日：2003-12-22

申请人： Yong-Fong Lee ,  Partha Kundu ,  Edward Grochowski

发明人： Yong-Fong Lee ,  Partha Kundu ,  Edward Grochowski

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/32 ,  G06F9/40

CPC分类号： G06F9/30105 ,  G06F9/30123 ,  G06F9/30134 ,  G06F9/4484

摘要： A method and apparatus for selectively storing a register stack onto a register stack backing store is disclosed. In one embodiment, a non-exclusive boundary is determined enclosing registers that were actually used (e.g. written to) by a function. The description of that boundary is saved, and only the contents of the registers within the boundary are saved to register stack backing store as part of a spill operation. When the function is later restored, the description of the boundary is recalled and used to support the loading of just those registers from the register stack backing store as part of a fill operation.

摘要翻译： 公开了一种用于将寄存器堆栈选择性地存储到寄存器堆栈后备存储器上的方法和装置。 在一个实施例中，确定包围实际使用（例如写入）功能的寄存器的非排他边界。 保存该边界的描述，只有边界内的寄存器的内容才能保存到寄存器堆栈后备存储中，作为溢出操作的一部分。 当函数稍后恢复时，边界的描述被调用并用于支持从寄存器堆栈后备存储器中仅加载这些寄存器作为填充操作的一部分。

公开(公告)号：US20050102494A1

公开(公告)日：2005-05-12

申请号：US10712618

申请日：2003-11-12

申请人： Edward Grochowski ,  Jeffrey Rupley ,  Partha Kundu

发明人： Edward Grochowski ,  Jeffrey Rupley ,  Partha Kundu

IPC分类号： G06F9/00 ,  G06F9/318

CPC分类号： G06F9/3017

摘要： Disclosed are embodiments of an apparatus, system, and method for implementing a register stack using micro-operations. A register stack engine generates a plurality of micro-operations to implement a memory operation in support of register windowing, such as spill or fill to/from a backing store. These micro-operations are inserted into an execution pipeline along with other micro-operations not related to register stack operation.

摘要翻译： 公开了用于使用微操作来实现寄存器堆栈的装置，系统和方法的实施例。 寄存器堆栈引擎产生多个微操作以实现支持寄存器窗口的存储器操作，诸如从后备存储器溢出或填充到后备存储器。 这些微操作与其他与寄存器堆栈操作无关的微操作被插入到执行流水线中。

公开(公告)号：US20050223199A1

公开(公告)日：2005-10-06

申请号：US10816103

申请日：2004-03-31

申请人： Edward Grochowski ,  Hong Wang ,  John Shen ,  Perry Wang ,  Jamison Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

发明人： Edward Grochowski ,  Hong Wang ,  John Shen ,  Perry Wang ,  Jamison Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/44

CPC分类号： G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

摘要翻译： 公开了提供用户级多线程的方法和系统。 根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。 一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。

公开(公告)号：US20070164787A1

公开(公告)日：2007-07-19

申请号：US11234548

申请日：2005-09-23

申请人： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien Lu ,  Murali Annavaram

发明人： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien Lu ,  Murali Annavaram

IPC分类号： H03K19/173 ,  G06F7/38

CPC分类号： G01R31/31922 ,  G01R31/31726 ,  H03K5/1534 ,  H04L7/0083 ,  H04L7/033

摘要： Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

摘要翻译： 两个锁存器在时钟信号的转变时存储数据信号的状态。 比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。 描述和要求保护使用锁存器和比较逻辑的系统。

公开(公告)号：US06938126B2

公开(公告)日：2005-08-30

申请号：US10121524

申请日：2002-04-12

申请人： Alejandro Ramirez ,  Edward Grochowski ,  Hong Wang ,  John Shen

发明人： Alejandro Ramirez ,  Edward Grochowski ,  Hong Wang ,  John Shen

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F12/0882 ,  G06F12/0886 ,  Y02D10/13

摘要： A method, apparatus, and system that compares a current fetch request having a first start address and length associated with the current fetch request to a second start address of the next fetch request, determines whether the content already loaded in a buffer will be used to at least partially fulfill the next fetch request based upon the comparison, and inhibits access to an instruction cache based upon the comparison.

摘要翻译： 将具有第一起始地址和与当前取出请求相关联的长度的当前提取请求与下一个提取请求的第二起始地址进行比较的方法，装置和系统确定已经加载在缓冲器中的内容是否将被用于 至少部分地基于比较来完成下一个提取请求，并且基于比较来禁止对指令高速缓存的访问。

公开(公告)号：US06904502B2

公开(公告)日：2005-06-07

申请号：US10743069

申请日：2003-12-23

申请人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

发明人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/16 ,  G11C7/24

CPC分类号： G06F12/0891

摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs using a blind invalidate circuit in high-speed memories. In accordance with an embodiment of the present invention, a tag array memory circuit including a plurality of memory bit circuits coupled together to form an n-bit memory cell; and a blind invalidate circuit coupled to a memory bit circuit in the n-bit memory cell, the blind invalidate circuit to clear a bit in the memory bit circuit, if a primary clear bit line is asserted and a received bit value of a right-adjacent memory bit circuit is zero.

摘要翻译： 本发明涉及高可靠性高性能微处理器的设计，更具体地涉及在高速存储器中使用盲目无效电路的设计。 根据本发明的实施例，一种标签阵列存储电路，包括耦合在一起以形成n位存储单元的多个存储器位电路; 以及与n位存储器单元中的存储器位电路耦合的盲目无效电路，盲目无效电路清除存储器位电路中的一位，如果主清零位线被断言，并且接收到的位值为右， 相邻的存储器位电路为零。

公开(公告)号：US06813628B2

公开(公告)日：2004-11-02

申请号：US09746771

申请日：2000-12-22

申请人： Bharat Bhushan ,  Edward Grochowski ,  Vinod Sharma ,  John Crawford

发明人： Bharat Bhushan ,  Edward Grochowski ,  Vinod Sharma ,  John Crawford

IPC分类号： G06F704

CPC分类号： G06F7/5095 ,  G06F7/02 ,  G06F7/026 ,  G06F7/48 ,  G06F7/4824

摘要： A method and apparatus is disclosed to compare numbers for equality. The numbers represented in a redundant form, including numbers received from a bypass circuit are subtracted. More specifically, a complemented form is generated and supplied to an arithmetic circuit for at least one number represented in the redundant form. Input to the arithmetic circuit is adjusted to augment a result generated through the arithmetic circuit to generate a valid outcome represented in the redundant form as a result of a subtraction operation. Results of the subtraction operation are compared to zero in redundant form using a non-propagative circuit and without requiring carry propagation, thereby producing an equality comparison of the number in redundant form.

摘要翻译： 公开了一种方法和装置，用于比较相等的数字。 减去以冗余形式表示的数字，包括从旁路电路接收的数字。更具体地，产生补码形式并将其提供给用冗余形式表示的至少一个数字的运算电路。 调整运算电路的输入以增加通过算术电路产生的结果，以产生作为减法运算的结果以冗余形式表示的有效结果。 使用非传播电路将减法操作的结果与冗余形式进行比较，而不需要进位传播，从而产生冗余形式的数量的等式比较。

公开(公告)号：US06775746B2

公开(公告)日：2004-08-10

申请号：US10435386

申请日：2003-05-12

申请人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

发明人： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC分类号： G06F1210

CPC分类号： G06F12/0891

摘要： The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.

公开(公告)号：US20170199825A1

公开(公告)日：2017-07-13

申请号：US15384054

申请日：2016-12-19

申请人： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

发明人： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC分类号： G06F12/1009 ,  G06F12/14 ,  G06F12/0864 ,  G06F12/1027

CPC分类号： G06F12/1009 ,  G06F12/0864 ,  G06F12/1027 ,  G06F12/145 ,  G06F2212/152 ,  G06F2212/6032 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/68

摘要： A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

公开(公告)号：US20130219399A1

公开(公告)日：2013-08-22

申请号：US13843164

申请日：2013-03-15

申请人： Hong Wang ,  John Shen ,  Edward Grochowski ,  Richard Hankins ,  Gautham Chinya ,  Bryant Bigbee ,  Shivnandan Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju Patel ,  James Held

发明人： Hong Wang ,  John Shen ,  Edward Grochowski ,  Richard Hankins ,  Gautham Chinya ,  Bryant Bigbee ,  Shivnandan Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju Patel ,  James Held

IPC分类号： G06F9/48

CPC分类号： G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

摘要： In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

摘要翻译： 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。