公开(公告)号：US6127267A

公开(公告)日：2000-10-03

申请号：US168670

申请日：1998-10-09

申请人： Yoshihisa Matsubara ,  Takashi Ishigami ,  Yoshiaki Yamada ,  Shinichi Watanuki

发明人： Yoshihisa Matsubara ,  Takashi Ishigami ,  Yoshiaki Yamada ,  Shinichi Watanuki

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/78 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518

摘要： A fabrication method of a semiconductor device is provided, which makes it possible to form a thin and elongated refractory-metal silicide layer while preventing the overgrowth phenomenon. This method is comprised of the steps (a) to (c). In the step (a), a first refractory metal film is formed on a silicon region. In the step (b), a second refractory metal film is formed on the first refractory metal film. The second refractory metal film contains a same refractory metal as the first refractory metal film and nitrogen. A stress of the second refractory metal film is controlled to be a specific value or lower. In the step (c), the first refractory metal film and the second refractory metal film are heat-treated in an atmosphere excluding nitrogen, thereby forming a refractory-metal silicide layer at an interface between the silicon region and the first refractory metal film due to silicidation reaction of the first refractory metal film with the silicon region. The value of the stress of the second refractory metal film is set so that the second refractory metal film applies substantially no effect to a plastic deformation of the refractory-metal silicide layer occurring during the silicidation reaction in the step (c).

摘要翻译： 提供了一种半导体器件的制造方法，其可以在防止过度生长现象的同时形成细长的难熔金属硅化物层。 该方法由步骤（a）至（c）组成。 在步骤（a）中，在硅区域上形成第一难熔金属膜。 在步骤（b）中，在第一难熔金属膜上形成第二难熔金属膜。 第二耐火金属膜含有与第一难熔金属膜相同的难熔金属和氮。 将第二难熔金属膜的应力控制在特定值以下。 在步骤（c）中，将第一难熔金属膜和第二难熔金属膜在不含氮的气氛中热处理，由此在硅区域与第一难熔金属膜之间的界面处形成难熔金属硅化物层，由此 使第一难熔金属膜与硅区域的硅化反应。 第二耐火金属膜的应力值被设定为使得第二耐火金属膜对于步骤（c）中的硅化反应期间发生的难熔金属硅化物层的塑性变形基本上没有影响。

公开(公告)号：US06241859B1

公开(公告)日：2001-06-05

申请号：US09138572

申请日：1998-08-24

申请人： Yoshiaki Yamada ,  Yoshihisa Matsubara ,  Takashi Ishigami

发明人： Yoshiaki Yamada ,  Yoshihisa Matsubara ,  Takashi Ishigami

IPC分类号： C23C1434

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28562 ,  H01L29/456 ,  H01L29/4933 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method of forming a silicide layer on a silicon region. The method comprises the following steps. A first refractory metal layer is formed on the silicon region. The first refractory metal layer is made of a first refractory metal. A second refractory metal layer is formed on the first refractory metal layer. The second refractory metal layer is made of a second refractory metal and containing nitrogen. The second refractory metal layer has a film stress of not higher than 1×1010 dyne/cm2. A heat treatment is carried out in a first atmosphere substantially free of nitrogen so as to cause a silicidation of a lower region of the first refractory metal layer, whereby a C49-structured refractory metal silicide layer is formed on the silicon region.

摘要翻译： 本发明提供一种在硅区上形成硅化物层的方法。 该方法包括以下步骤。 在硅区域上形成第一难熔金属层。 第一耐火金属层由第一耐火金属制成。 在第一难熔金属层上形成第二难熔金属层。 第二耐火金属层由第二难熔金属制成并含有氮。 第二难熔金属层的膜应力不高于1×10 10达因/ cm 2。 在基本上不含氮的第一气氛中进行热处理，以使第一难熔金属层的下部区域发生硅化，由此在硅区域上形成C49结构的难熔金属硅化物层。

公开(公告)号：US06091081A

公开(公告)日：2000-07-18

申请号：US982585

申请日：1997-12-02

申请人： Yoshihisa Matsubara ,  Ko Noguchi ,  Shinya Ito ,  Noriaki Oda ,  Akira Matsumoto ,  Takashi Ishigami ,  Masahiko Nakamae ,  Tadahiko Horiuchi ,  Kazuhiko Endo ,  Toru Tatsumi ,  Yoshishige Matsumoto

发明人： Yoshihisa Matsubara ,  Ko Noguchi ,  Shinya Ito ,  Noriaki Oda ,  Akira Matsumoto ,  Takashi Ishigami ,  Masahiko Nakamae ,  Tadahiko Horiuchi ,  Kazuhiko Endo ,  Toru Tatsumi ,  Yoshishige Matsumoto

IPC分类号： H01L21/302 ,  H01L21/205 ,  H01L21/3065 ,  H01L21/312 ,  H01L21/314 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L31/0312

CPC分类号： H01L21/76834 ,  H01L21/312 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76832 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002

摘要： A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.

摘要翻译： 公开了在布线层和使用这种膜的半导体器件之间使用的低介电常数层间绝缘膜的结构和制造工艺。 可以在实际工艺中承受的绝缘膜包括无定形氟化碳膜。 在无定形氟化碳膜的两侧设置有类金刚石碳膜和硅过剩层，以插入布线层之间，从而显着提高与布线的接合和与其接触的另一绝缘膜。 此外，将硅基绝缘膜设置并平坦化在含有埋设有布线层的无定形氟化碳膜的多层膜上，并且用作用于各向异性蚀刻类金刚石碳膜和无定形氟化碳膜的硬掩模， 氧等离子体形成通孔。

公开(公告)号：US06372628B1

公开(公告)日：2002-04-16

申请号：US09579474

申请日：2000-05-26

申请人： Yoshihisa Matsubara ,  Ko Noguchi ,  Shinya Ito ,  Noriaki Oda ,  Akira Matsumoto ,  Takashi Ishigami ,  Masahiko Nakamae ,  Tadahiko Horiuchi ,  Kazuhiko Endo ,  Toru Tatsumi ,  Yoshishige Matsumoto

发明人： Yoshihisa Matsubara ,  Ko Noguchi ,  Shinya Ito ,  Noriaki Oda ,  Akira Matsumoto ,  Takashi Ishigami ,  Masahiko Nakamae ,  Tadahiko Horiuchi ,  Kazuhiko Endo ,  Toru Tatsumi ,  Yoshishige Matsumoto

IPC分类号： H01L214763

CPC分类号： H01L21/02118 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/312 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and manufacturing process of a low dielectric constant interlayer insulating film used between wiring layers and semiconductor devices using such film are disclosed. The insulating film which can withstand in an actual process comprises an amorphous carbon fluoride film. A diamond like carbon film and a silicon excess layer are disposed on both sides of the amorphous carbon fluoride film to be inserted between the wiring layers, whereby adhesion to wiring and another insulating film contacting it is significantly enhanced. In addition, a silicon based insulating film is disposed and flattened on a multilayer film containing an amorphous carbon fluoride film buried with a wiring layer, and is used as a hard mask for anisotropically etching the diamond like carbon film and the amorphous carbon fluoride film with oxygen plasma to form a via hole.

摘要翻译： 公开了在布线层和使用这种膜的半导体器件之间使用的低介电常数层间绝缘膜的结构和制造工艺。 可以在实际工艺中承受的绝缘膜包括无定形氟化碳膜。 在无定形氟化碳膜的两侧设置有类金刚石碳膜和硅过剩层，以插入布线层之间，从而显着提高与布线的接合和与其接触的另一绝缘膜。 另外，将硅基绝缘膜设置并平坦化在含有埋设有布线层的无定形氟化碳膜的多层膜上，并且用作用于各向异性蚀刻金刚石状碳膜和无定形氟化碳膜的硬掩模， 氧等离子体形成通孔。

公开(公告)号：US08664010B2

公开(公告)日：2014-03-04

申请号：US12929966

申请日：2011-02-28

申请人： Yoshihisa Matsubara

发明人： Yoshihisa Matsubara

IPC分类号： H01L21/428

CPC分类号： H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： An MTJ element is formed in a wiring layer located in a lower tier and yet application of heat to the MTJ element is suppressed. A first insulating layer is formed over a substrate. Subsequently, the MTJ element is formed over the first insulating layer. After that a first wiring is formed over the MTJ element. Thereafter, a second insulating layer is formed over the first wiring. Then a second wiring is formed in the superficial layer of the second insulating layer. The second wiring is heat treated by photoirradiation. A shield conductor is formed at the step of forming the second wiring.

摘要翻译： MTJ元件形成在位于下层的布线层中，并且对MTJ元件施加热量被抑制。 第一绝缘层形成在衬底上。 随后，在第一绝缘层上形成MTJ元件。 之后，在MTJ元件上形成第一布线。 此后，在第一布线上形成第二绝缘层。 然后在第二绝缘层的表层形成第二布线。 第二个布线通过光照射进行热处理。 在形成第二布线的步骤中形成屏蔽导体。

公开(公告)号：US07989952B2

公开(公告)日：2011-08-02

申请号：US12453688

申请日：2009-05-19

申请人： Yoshihisa Matsubara

发明人： Yoshihisa Matsubara

IPC分类号： H01L23/48

CPC分类号： H01L23/535 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having macro circuit including a plurality of fine interconnections, an extension interconnection wider than the fine interconnections, having a first end connected to one or more of the fine interconnections and a second end located in an area of the semiconductor device external to the macro circuit, and one or more of the fine interconnections widened towards the connection to the extension wiring interconnection. The extension interconnection is formed in the same layer as one or more of the interconnections connected to the extension interconnection.

摘要翻译： 一种具有宏电路的半导体器件，包括多个精细互连，比微细互连更宽的扩展互连，具有连接到一个或多个精细互连的第一端和位于半导体器件外部的半导体器件的区域中的第二端 宏电路，并且一个或多个精细互连朝着与延伸布线互连的连接加宽。 扩展互连形成在与连接到扩展互连的互连中的一个或多个相同的层中。

公开(公告)号：US07785986B2

公开(公告)日：2010-08-31

申请号：US12400892

申请日：2009-03-10

申请人： Yoshihisa Matsubara ,  Hiromichi Suzuki ,  Wahei Kitamura ,  Kosho Akiyama ,  Seiji Kato

发明人： Yoshihisa Matsubara ,  Hiromichi Suzuki ,  Wahei Kitamura ,  Kosho Akiyama ,  Seiji Kato

IPC分类号： H01L21/30 ,  H01L23/34

CPC分类号： H01L21/67333 ,  H01L2924/0002 ,  H01L2924/00

摘要： To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.

摘要翻译： 为了防止半导体芯片在运输期间粘附到托盘，采用以下状态传输半导体芯片的方法。 当具有多个具有用于在其主表面上容纳半导体芯片的凹入截面的容纳部分的托盘被堆叠成多级时，半导体芯片被容纳在形成在主表面上的容纳部分所形成的空间中 下级托盘和形成在上级托盘的后表面上的相应的容纳部分。 这里，在形成在上层托盘的后表面上的容纳部分的底表面上，以散射方式布置具有防止突起与半导体芯片接触的高度的隔离突起。 以这种方式，可以防止半导体芯片粘附到上层托盘的后表面。

公开(公告)号：US20090302451A1

公开(公告)日：2009-12-10

申请号：US12453931

申请日：2009-05-27

申请人： Yoshihisa Matsubara

发明人： Yoshihisa Matsubara

IPC分类号： H01L23/48 ,  H01L23/488 ,  H01L23/02

CPC分类号： H01L23/5382 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a semiconductor chip, a wiring substrate, and wires. The semiconductor chip includes a first circuit, a second circuit having a function differing from that of the first circuit, a plurality of first pads disposed in a row along one side of the semiconductor chip and connected to the first circuit, and a plurality of second pads disposed between both of the first and second circuits and the first pads, and connected to the second circuit. The wiring substrate includes a plurality of terminals and the plurality of wires is connected between a plurality of terminals provided outside of the semiconductor chip, and ones of the first pads and the second pads. The wires are free from the other of the first pads and the second pads, and the plurality of the wires being not intersected to each other.

摘要翻译： 半导体器件包括半导体芯片，布线基板和布线。 半导体芯片包括第一电路，具有与第一电路的功能不同的功能的第二电路，沿着半导体芯片的一侧并排连接到第一电路的多个第一焊盘以及多个第二焊盘 设置在第一和第二电路两者之间的焊盘和第一焊盘，并连接到第二电路。 布线基板包括多个端子，并且多个导线连接在设置在半导体芯片外部的多个端子之间，以及第一焊盘和第二焊盘中的一个。 导线与第一焊盘和第二焊盘中的另一个无接触，并且多个电线彼此不相交。

公开(公告)号：US20090159978A1

公开(公告)日：2009-06-25

申请号：US12345015

申请日：2008-12-29

申请人： Yoshihisa Matsubara ,  Takashi Sakoh

发明人： Yoshihisa Matsubara ,  Takashi Sakoh

IPC分类号： H01L29/78 ,  H01L21/322

CPC分类号： H01L21/823842 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10894 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： A semiconductor device 100 includes a first gate 210, which is formed using a gate last process. The first gate 210 includes a gate insulating film formed in a bottom surface in a first concave portion formed in the insulating film; a gate electrode formed over the gate insulating film in the first concave portion; and a protective insulating film 140 formed on the gate electrode in the first concave portion. In addition, the semiconductor device 100 includes a contact 134, which is coupled to the N-type impurity-diffused region 116a in the both sides of the first gate 210 and is buried in the second concave portion having a diameter that is large than the first concave portion.

摘要翻译： 半导体器件100包括使用门最后工艺形成的第一栅极210。 第一栅极210包括形成在形成在绝缘膜中的第一凹部中的底面中的栅极绝缘膜; 在所述第一凹部中形成在所述栅极绝缘膜上方的栅电极; 以及形成在第一凹部中的栅电极上的保护绝缘膜140。 此外，半导体器件100包括触点134，该触点134耦合到第一栅极210的两侧中的N型杂质扩散区域116a，并且被埋在第二凹部中，该第二凹部的直径大于 第一凹部。

公开(公告)号：US07504315B2

公开(公告)日：2009-03-17

申请号：US11007185

申请日：2004-12-09

申请人： Yoshihisa Matsubara ,  Hiromichi Suzuki ,  Wahei Kitamura ,  Kosho Akiyama ,  Seiji Kato

发明人： Yoshihisa Matsubara ,  Hiromichi Suzuki ,  Wahei Kitamura ,  Kosho Akiyama ,  Seiji Kato

IPC分类号： H01L21/30

CPC分类号： H01L21/67333 ,  H01L2924/0002 ,  H01L2924/00

摘要： To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.

摘要翻译： 为了防止半导体芯片在运输期间粘附到托盘，采用以下状态传输半导体芯片的方法。 当具有多个具有用于在其主表面上容纳半导体芯片的凹入截面的容纳部分的托盘被堆叠成多级时，半导体芯片被容纳在形成在主表面上的容纳部分所形成的空间中 下级托盘和形成在上级托盘的后表面上的相应的容纳部分。 这里，在形成在上层托盘的后表面上的容纳部分的底表面上，以散射方式布置具有防止突起与半导体芯片接触的高度的隔离突起。 以这种方式，可以防止半导体芯片粘附到上层托盘的后表面。