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    Semiconductor memory device having an SRAM and a DRAM on a single chip
    5.
    发明授权
    Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
    在单个芯片上具有SRAM和DRAM的半导体存储器件

    公开(公告)号：US06735141B2

    公开(公告)日：2004-05-11

    申请号：US09917913

    申请日：2001-07-31

    申请人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    发明人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    IPC分类号： G11C700

    CPC分类号： G11C11/005

    摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

    摘要翻译： 半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。 在芯片上提供DRAM，DRAM包括DRAM单元阵列。 地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值 ，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

    Method for operating a semiconductor memory device having a plurality of operating modes for controlling an internal circuit
    6.
    发明授权
    Method for operating a semiconductor memory device having a plurality of operating modes for controlling an internal circuit 有权
    一种用于操作具有用于控制内部电路的多种操作模式的半导体存储器件的方法

    公开(公告)号：US06629224B1

    公开(公告)日：2003-09-30

    申请号：US09562739

    申请日：2000-05-01

    申请人： Takaaki Suzuki ,  Toshiya Uchida ,  Kotoku Sato ,  Yoshimasa Yagishita

    发明人： Takaaki Suzuki ,  Toshiya Uchida ,  Kotoku Sato ,  Yoshimasa Yagishita

    IPC分类号： G06F1200

    CPC分类号： G11C11/406 ,  G11C5/066 ,  G11C11/40603 ,  G11C11/40611

    摘要： Signals supplied to predetermined terminals are accepted as commands at a plurality of times, the number of operating modes is sequentially narrowed down based on the command each time and an internal circuit is controlled according to the narrowed operating modes. Since the information necessary for determining an operating mode is accepted at a plurality of times, the number of terminals necessary for inputting commands can be reduced. In particular, in case of inputting commands at a dedicated terminal, its input pads, input circuits, or the like are no longer be required so that the chip size can be reduced. The reduction is accomplished by reducing the number of terminals, which gives limits to the package size. The command controlling circuit with a plurality of accepting circuits is comprised. Each of the accepting circuits respectively accepts signals, supplied at a plurality of times, each time. In other words, in accordance with the timing of the signal supplement, a different accepting circuit is respectively operated and the internal circuit is controlled. Accordingly, a command controlling circuit may be readily designed even in the semiconductor memory device having a complicated command combination. Consequently, it is able to facilitate the verification of the design.

    摘要翻译： 提供给预定端子的信号被多次接受为命令，每次基于该命令并且根据变窄的操作模式控制内部电路，操作模式的数量依次变窄。 由于多次接受确定操作模式所需的信息，因此可以减少输入命令所需的终端数量。 特别地，在专用端子输入命令的情况下，不再需要其输入焊盘，输入电路等，从而可以减小芯片尺寸。 通过减少端子数量来实现减少，这限制了封装尺寸。 包括具有多个接受电路的指令控制电路。 每个接收电路分别接收每次多次提供的信号。 换句话说，根据信号补充的定时，分别操作不同的接受电路，并且控制内部电路。 因此，即使在具有复杂的指令组合的半导体存储器件中，也可以容易地设计指令控制电路。 因此，它能够方便验证设计。

    Semiconductor memory device having an SRAM and a DRAM on a single chip
    8.
    发明授权
    Semiconductor memory device having an SRAM and a DRAM on a single chip 失效
    在单个芯片上具有SRAM和DRAM的半导体存储器件

    公开(公告)号：US06292426B1

    公开(公告)日：2001-09-18

    申请号：US09531498

    申请日：2000-03-21

    申请人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    发明人： Hitoshi Ikeda ,  Akihiro Funyu ,  Shinya Fujioka ,  Takaaki Suzuki ,  Masao Taguchi ,  Kimiaki Satoh ,  Kotoku Sato

    IPC分类号： G11C800

    CPC分类号： G11C11/005

    摘要： A semiconductor memory device includes an SRAM provided on a chip, the SRAM including an SRAM cell array. A DRAM is provided on the chip, the DRAM including a DRAM cell array. An address input circuit receives an address signal, the address signal having a first portion and a second portion, the first portion carrying a unique value of row-column address information provided to access one of memory locations in one of the SRAM and DRAM cell arrays, the second portion carrying a unique value of SRAM/DRAM address information provided to select one of the SRAM and the DRAM.

    摘要翻译： 半导体存储器件包括设置在芯片上的SRAM，SRAM包括SRAM单元阵列。 在芯片上提供DRAM，DRAM包括DRAM单元阵列。 地址输入电路接收地址信号，地址信号具有第一部分和第二部分，第一部分承载提供用于访问SRAM和DRAM单元阵列之一中的存储单元之一的行列地址信息的唯一值 ，第二部分承载提供用于选择SRAM和DRAM之一的SRAM / DRAM地址信息的唯一值。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US6144616A

    公开(公告)日：2000-11-07

    申请号：US429472

    申请日：1999-10-29

    申请人： Takaaki Suzuki ,  Kotoku Sato

    发明人： Takaaki Suzuki ,  Kotoku Sato

    IPC分类号： G11C7/00 ,  G11C7/10

    CPC分类号： G11C7/1072

    摘要： A semiconductor memory device operating in synchronism with a clock includes an address latch&comparator part latching a first address signal associated with a write command and comparing the first address signal with a second address signal associated with a read command. A write data buffer part holds a data signal associated with the write command. The data signal held in the write data buffer part is read as a data signal requested by the read command when the first and second address signals coincide with each other.

    摘要翻译： 与时钟同步工作的半导体存储器件包括地址锁存器和比较器部件，其锁存与写入命令相关联的第一地址信号，并将第一地址信号与与读取命令相关联的第二地址信号进行比较。 写数据缓冲器部分保存与写命令相关联的数据信号。 当第一和第二地址信号彼此一致时，保持在写入数据缓冲器部分中的数据信号被读取为由读取命令请求的数据信号。