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公开(公告)号：US06522182B2
公开(公告)日：2003-02-18
申请号：US09385008
申请日：1999-08-27
申请人： Hiroyoshi Tomita , Naoharu Shinozaki , Nobutaka Taniguchi , Waichirou Fujieda , Yasuharu Sato , Kenichi Kawasaki , Masafumi Yamazaki , Kazuhiro Ninomiya
发明人： Hiroyoshi Tomita , Naoharu Shinozaki , Nobutaka Taniguchi , Waichirou Fujieda , Yasuharu Sato , Kenichi Kawasaki , Masafumi Yamazaki , Kazuhiro Ninomiya
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G11C7/1072 , G11C7/222 , H03K5/131
摘要： In the present invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit in the phase comparison circuit of the DLL circuit. Also, by connecting the first external earthing power source to the variable delay circuit and/or phase coincidence detection unit, the effect of power source noise from the second external earthing power source originating from the operation of circuits other than these is suppressed.
摘要翻译： 在本发明中，提供给集成电路装置的外部电源被分成用于DLL电路的第一外部电源和除了DLL电路以外的电路的第二外部电源。 根据本发明，通过利用第一外部电源优选用于DLL电路的可变延迟电路，而将第二外部电源中产生的电源噪声不能传输到可变延迟电路，甚至更优选地用于 其延迟单位。 此外，优选地，通过利用DLL电路的相位比较电路中的相位一致检测单元的第一电源，将第二外部电源中产生的电源噪声不能发送到相位一致检测单元。 此外，通过将第一外部接地电源连接到可变延迟电路和/或相位一致检测单元，抑制源于除了这些以外的电路的操作的来自第二外部接地电源的电源噪声的影响。
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公开(公告)号：US06181174B2
公开(公告)日：2001-01-30
申请号：US09404221
申请日：1999-09-23
IPC分类号： H03L706
CPC分类号： H03L7/0805 , G06F1/08 , G06F1/10 , G11C7/1039 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/133 , H03K23/58 , H03L7/0814
摘要： A semiconductor integrated circuit device includes a DLL circuit. The DLL circuit includes a frequency divider which frequency-divides an input clock at a frequency dividing ratio which is varied depending on a frequency of the input clock and thus results in a dummy clock and a reference clock. A delay system includes a variable delay circuit which delays the dummy clock. A control circuit controls a delay amount of the variable delay circuit so that a phase of a delayed dummy clock from the delay system and the reference clock becomes zero.
摘要翻译： 半导体集成电路装置包括DLL电路。 DLL电路包括分频器，该分频器以分频比对输入时钟进行分频，该分频比根据输入时钟的频率而变化，从而产生虚拟时钟和参考时钟。 延迟系统包括延迟虚拟时钟的可变延迟电路。 控制电路控制可变延迟电路的延迟量，使得来自延迟系统和参考时钟的延迟的虚拟时钟的相位变为零。
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公开(公告)号：US06459641B2
公开(公告)日：2002-10-01
申请号：US09834945
申请日：2001-04-16
申请人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
发明人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/065
摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.
摘要翻译： 本发明的目的在于提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。 根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据 选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元， 生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。
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公开(公告)号：US06246620B1
公开(公告)日：2001-06-12
申请号：US09533759
申请日：2000-03-23
申请人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
发明人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C2207/005 , G11C2207/065
摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.
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公开(公告)号：US06188640B1
公开(公告)日：2001-02-13
申请号：US09398828
申请日：1999-09-17
IPC分类号： G11C800
CPC分类号： G11C7/106 , G11C7/1051 , G11C7/1069 , G11C7/1072 , G11C7/22 , G11C11/4093
摘要： A data output circuit for a semiconductor memory device, such as a synchronous DRAM (SDRAM) includes an output control circuit that acquires a command in sync with an input internal clock signal and generates an output control signal used to determine the output timing of a data signal. An output buffer receives the output control signal and then outputs the data signal in accordance with an output internal clock signal. The phase of the output internal clock signal is advanced from that of the input internal clock signal. The output control circuit also includes a latency counter that generates the output control signal by counting the cycles of a second output internal clock signal, which is delayed from the first output internal clock signal.
摘要翻译： 用于诸如同步DRAM（SDRAM）的半导体存储器件的数据输出电路包括输出控制电路，其获取与输入的内部时钟信号同步的命令，并且生成用于确定数据的输出定时的输出控制信号 信号。 输出缓冲器接收输出控制信号，然后根据输出内部时钟信号输出数据信号。 输出内部时钟信号的相位从输入内部时钟信号的相位提前。 输出控制电路还包括延迟计数器，其通过对从第一输出内部时钟信号延迟的第二输出内部时钟信号的周期进行计数来产生输出控制信号。
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公开(公告)号：US6088291A
公开(公告)日：2000-07-11
申请号：US147600
申请日：1999-01-29
申请人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
发明人： Shinya Fujioka , Masao Taguchi , Waichirou Fujieda , Yasuharu Sato , Takaaki Suzuki , Tadao Aikawa , Takayuki Nagasawa
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C11/408 , G11C11/4091 , G11C11/4094 , G11C7/00
CPC分类号： G11C7/06 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C7/1039 , G11C7/1072 , G11C7/12 , G11C8/00 , G11C8/08 , G11C8/10 , G11C2207/005 , G11C2207/065
摘要： The present invention is aimed at providing a semiconductor memory device which performs a row-address pipe-line operation in accessing different row addresses so as to achieve high-speed access. The semiconductor memory device according to the present invention includes a plurality of sense-amplifiers which store data when the data is received via bit lines from memory cells corresponding to a selected word line, a column decoder which reads parallel data of a plurality of bits from selected sense amplifiers by simultaneously selecting a plurality of column gates in response to a column address, a data-conversion unit which converts the parallel data into serial data, and a precharge-signal-generation unit which generates an internal precharge signal a first delay-time period after generation of a row-access signal for selecting the selected word line so as to reset the bit lines and said plurality of sense-amplifiers.
摘要翻译： PCT No.PCT / JP98 / 02443 Sec。 371日期1999年1月29日第 102（e）日期1999年1月29日PCT提交1998年6月3日PCT公布。 第WO98 / 56004号公报 日期：1998年12月10日本发明旨在提供一种在访问不同行地址时执行行地址管线操作以实现高速访问的半导体存储器件。 根据本发明的半导体存储器件包括多个读出放大器，当经由位线从存储器单元接收数据时存储数据，该存储器单元对应于所选择的字线，列解码器从多个位读取多个位的并行数据 选择的读出放大器，通过响应于列地址同时选择多个列门，将并行数据转换为串行数据的数据转换单元，以及产生内部预充电信号的预充电信号产生单元， 生成用于选择所选字线的行访问信号以便复位位线和所述多个感测放大器之后的时间段。
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公开(公告)号：US06191999B1
公开(公告)日：2001-02-20
申请号：US08993139
申请日：1997-12-18
申请人： Waichirou Fujieda , Shinya Fujioka , Tadao Aikawa
发明人： Waichirou Fujieda , Shinya Fujioka , Tadao Aikawa
IPC分类号： G11C800
摘要： A semiconductor memory device using hierarchical word decoding for word selection includes memory-cell areas, each of which is provided for a corresponding one of column blocks. The semiconductor memory device further includes sub-word lines provided for each one of the column blocks and extending over a corresponding one of the memory-cell areas, and sub-word decoders provided on either side of a given one of the memory-cell areas to select one of the sub-word lines only with respect to the given one of the memory-cell areas.
摘要翻译： 使用用于字选择的分层字解码的半导体存储器件包括存储单元区域，每个区域被提供给相应的列块。 半导体存储器件还包括为每个列块提供的子字线，并且在相应的一个存储单元区域上延伸，并且在给定的一个存储单元区域的两侧提供的子字解码器 仅相对于给定的一个存储单元区域来选择一个子字线。
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