公开(公告)号：US5901101A

公开(公告)日：1999-05-04

申请号：US919505

申请日：1997-08-28

申请人： Takaaki Suzuki ,  Masao Nakano ,  Hiroyoshi Tomita ,  Yasuharu Sato ,  Kotoku Sato ,  Nobutaka Taniguchi

发明人： Takaaki Suzuki ,  Masao Nakano ,  Hiroyoshi Tomita ,  Yasuharu Sato ,  Kotoku Sato ,  Nobutaka Taniguchi

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C11/406

摘要： In a semiconductor memory device operable in synchronism with a clock signal externally supplied thereto, there are provided a first part which detects a state of a predetermined signal after a given command is input to the semiconductor memory; and a second part which sets, on the basis of the state of the predetermined signal, the semiconductor memory device to a self-refresh mode in which a refresh operation is carried out without an external signal.

摘要翻译： 在与外部提供给其的时钟信号同步操作的半导体存储器件中，提供了第一部分，其在将给定命令输入到半导体存储器之后检测预定信号的状态; 以及第二部分，其基于预定信号的状态将半导体存储器件设置为在没有外部信号的情况下执行刷新操作的自刷新模式。

公开(公告)号：US6078514A

公开(公告)日：2000-06-20

申请号：US61023

申请日：1998-04-16

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Takaaki Suzuki ,  Hiroyoshi Tomita ,  Toshiya Uchida ,  Yasuharu Sato ,  Atsushi Hatakeyama ,  Masato Matsumiya ,  Yasurou Matsuzaki

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Takaaki Suzuki ,  Hiroyoshi Tomita ,  Toshiya Uchida ,  Yasuharu Sato ,  Atsushi Hatakeyama ,  Masato Matsumiya ,  Yasurou Matsuzaki

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H01L21/60 ,  H01L25/00 ,  H01L27/10 ,  H01L25/04 ,  H01L23/36

CPC分类号： H01L23/60 ,  G11C7/1006 ,  G11C7/22 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L24/48 ,  H01L27/0266 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/30105

摘要： A semiconductor system includes at least one logic chip and at least one memory chip arranged such that one side of the at least one memory chip faces one side of the at least one logic chip. The semiconductor system further includes first input/output nodes, provided for the at least one logic chip, for data transfer with an adjacent memory chip, second input/output nodes, provided for the at least one memory chip, for data transfer with an adjacent logic chip, and a package housing the at least one logic chip and the at least one memory chip, wherein the first input/output nodes are arranged along the one side of the at least one logic chip, and the second input/output nodes are arranged along the one side of the at least one memory chip.

摘要翻译： 半导体系统包括至少一个逻辑芯片和布置成使得至少一个存储器芯片的一侧面向至少一个逻辑芯片的一侧的至少一个存储器芯片。 所述半导体系统还包括为所述至少一个逻辑芯片提供的用于与相邻存储器芯片进行数据传输的第一输入/输出节点，为所述至少一个存储器芯片提供的第二输入/输出节点，用于与相邻的 逻辑芯片以及容纳所述至少一个逻辑芯片和所述至少一个存储器芯片的封装，其中所述第一输入/输出节点沿着所述至少一个逻辑芯片的一侧布置，并且所述第二输入/输出节点是 沿着至少一个存储器芯片的一侧布置。

公开(公告)号：US06397312B1

公开(公告)日：2002-05-28

申请号：US08970086

申请日：1997-11-13

申请人： Masao Nakano ,  Hiroyoshi Tomita ,  Kotoku Sato ,  Yoshihiro Takemae ,  Masao Taguchi

发明人： Masao Nakano ,  Hiroyoshi Tomita ,  Kotoku Sato ,  Yoshihiro Takemae ,  Masao Taguchi

IPC分类号： G06F1200

CPC分类号： G06F13/4243

摘要： A memory system having a simple configuration capable of high-speed data transmission is disclosed. Data is output from a controller or a memory in synchronism with a clock or a data strobe signal. The clock or the data strobe signal is transmitted by a clock signal line or a data strobe signal line, respectively, arranged in parallel to a data signal line. A delay circuit delays by a predetermined time the signals transmitted through the clock signal line or the data strobe signal line. The clock or the data strobe signal thus assumes a phase suitable for retrieval at the destination, so that the data signal can be retrieved directly by means of the received clock or the received data strobe signal.

摘要翻译： 公开了一种具有能够进行高速数据传输的简单配置的存储器系统。 与时钟或数据选通信号同步地从控制器或存储器输出数据。 时钟或数据选通信号分别通过与数据信号线并联布置的时钟信号线或数据选通信号线来发送。 延迟电路在预定时间内延迟通过时钟信号线或数据选通信号线发送的信号。 因此，时钟或数据选通信号采取适合在目的地检索的相位，使得可以通过接收的时钟或接收的数据选通信号直接检索数据信号。

公开(公告)号：US6154405A

公开(公告)日：2000-11-28

申请号：US924315

申请日：1997-09-05

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Hirohiko Mochizuki ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Tadao Aikawa

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Hirohiko Mochizuki ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Tadao Aikawa

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4096 ,  G11C7/02

CPC分类号： G11C11/4096 ,  G11C7/1048 ,  G11C7/12

摘要： A semiconductor memory device includes memory cells, word lines connected to the memory cells, bit lines connected to the memory cells, and a first circuit which resets the bit lines to a reset potential which is based on data read in a previous read cycle.

摘要翻译： 半导体存储器件包括存储器单元，连接到存储器单元的字线，连接到存储器单元的位线，以及基于在先前读取周期中读取的数据将位线复位到复位电位的第一电路。

公开(公告)号：US6028816A

公开(公告)日：2000-02-22

申请号：US924705

申请日：1997-09-05

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima ,  Masao Nakano

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima ,  Masao Nakano

IPC分类号： G06F13/42 ,  G06F1/10 ,  G06F1/12 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4093 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/00 ,  H03L7/081 ,  H04L7/00 ,  G11C8/00

CPC分类号： H03L7/0805 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/133 ,  H03K5/135 ,  H03L7/00 ,  H03L7/0814 ,  G11C2207/108

摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

公开(公告)号：US6063640A

公开(公告)日：2000-05-16

申请号：US30349

申请日：1998-02-25

申请人： Masataka Mizukoshi ,  Hidehiko Akasaki ,  Masao Nakano ,  Yasuhiro Fujii ,  Shinnosuke Kamata ,  Makoto Yanagisawa ,  Yasurou Matsuzaki ,  Toyonobu Yamada ,  Masami Matsuoka ,  Hiroyoshi Tomita

发明人： Masataka Mizukoshi ,  Hidehiko Akasaki ,  Masao Nakano ,  Yasuhiro Fujii ,  Shinnosuke Kamata ,  Makoto Yanagisawa ,  Yasurou Matsuzaki ,  Toyonobu Yamada ,  Masami Matsuoka ,  Hiroyoshi Tomita

IPC分类号： H01L23/58 ,  G01R31/26 ,  H01L21/66

CPC分类号： H01L22/32 ,  H01L22/22 ,  H01L2224/05554 ,  Y10S438/977

摘要： A semiconductor wafer testing method includes a pre-test step for forming a temporary test film on a surface of a semiconductor wafer, a test step for testing the semiconductor wafer by applying a probe to the temporary test film and a post-test step for exfoliating the temporary test film from the surface of the semiconductor wafer. The temporary test film includes test electrode groups each provided with a plurality of regularly arranged test electrodes, and wiring patterns for electrically connecting the test electrodes with corresponding ones of semiconductor unit electrodes in respective semiconductor units on the semiconductor wafer. Probe pins of said probe are arranged so as to be aligned with corresponding ones of the test electrodes of the respective test electrode groups.

摘要翻译： 半导体晶片测试方法包括：在半导体晶片的表面上形成临时测试膜的预测试步骤，通过向临时测试膜施加探针来测试半导体晶片的测试步骤和用于去角质的后测试步骤 来自半导体晶片表面的临时测试膜。 临时测试膜包括各自设置有多个规则排列的测试电极的测试电极组和用于将测试电极与半导体晶片上的各个半导体单元中的相应半导体单元电极电连接的布线图案。 所述探针的探头针布置成与各个测试电极组的相应测试电极对齐。

公开(公告)号：US06498524B1

公开(公告)日：2002-12-24

申请号：US09706731

申请日：2000-11-07

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC分类号： H03L708

CPC分类号： G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

摘要翻译： 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US06298004B1

公开(公告)日：2001-10-02

申请号：US08892790

申请日：1997-07-15

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC分类号： G11C800

CPC分类号： G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

摘要翻译： 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US20050242864A1

公开(公告)日：2005-11-03

申请号：US11055784

申请日：2005-02-11

申请人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

发明人： Kenichi Kawasaki ,  Yasuharu Sato ,  Terumasa Kitahara ,  Masao Nakano ,  Masao Taguchi ,  Yoshihiro Takemae ,  Yasurou Matsuzaki ,  Koichi Nishimura ,  Yoshinori Okajima ,  Naoharu Shinozaki ,  Hiroko Douchi

IPC分类号： G06F13/42 ,  G11C7/10 ,  G11C7/22 ,  H03H11/26 ,  H03K5/00 ,  H03K5/13 ,  H03L7/081

CPC分类号： G11C7/106 ,  G06F13/4243 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/002 ,  G11C2207/108 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814

摘要： Disclosed is a semiconductor device for outputting an output signal with a given phase held relative to an external clock despite a difference in characteristic, a change in temperature, and a fluctuation in supply voltage. The semiconductor device comprises an input circuit for inputting the external clock and outputting a reference signal, an output circuit for receiving an output timing signal and outputting an output signal according to the timing of the output timing signal, and an output timing control circuit for controlling the output timing so that the output signal exhibits a given phase relative to the external clock. The output timing control circuit includes a delay circuit for delaying the reference signal by a specified magnitude and generating an output timing signal, a phase comparison circuit for comparing the phase of the output timing signal with the phase of the reference signal, and a delay control circuit for specifying the magnitude of a delay to be produced by the delay circuit according to the result of comparison performed by the phase comparison circuit.

摘要翻译： 公开了一种用于输出具有相对于外部时钟保持的给定相位的输出信号的半导体器件，尽管特性差，温度变化和电源电压波动。 该半导体器件包括用于输入外部时钟并输出参考信号的输入电路，用于接收输出定时信号并根据输出定时信号的定时输出输出信号的输出电路和用于控制的输出定时控制电路 输出定时，使得输出信号相对于外部时钟呈现给定的相位。 输出定时控制电路包括用于将参考信号延迟指定幅度并产生输出定时信号的延迟电路，用于将输出定时信号的相位与参考信号的相位进行比较的相位比较电路和延迟控制 电路，用于根据由相位比较电路执行的比较结果来指定由延迟电路产生的延迟的大小。

公开(公告)号：US5640359A

公开(公告)日：1997-06-17

申请号：US686385

申请日：1996-07-25

申请人： Takaaki Suzuki ,  Yoshihiro Takemae ,  Masao Nakano

发明人： Takaaki Suzuki ,  Yoshihiro Takemae ,  Masao Nakano

IPC分类号： G11C11/407 ,  G11C8/08 ,  G11C8/14 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C8/14 ,  G11C8/08

摘要： The present invention relates to a word driver circuit provided in a memory circuit. The word driver circuit comprises a P channel and an N channel transistor having a gate electrode commonly connected and one source or drain electrode commonly connected. The N channeltransistor has another source or drain electrode connected to a ground. A word line is connected to the commonly connected source or drain electrode of the transistors. A first selection signal, generated by decoding a first group of address signals, whose potential is either a first potential by which the N channel transistor is rendered conductive or a second potential lower than the first power supply is supplied to the gate electrodes. And a second selection signal, generated by decoding a second group of address signals, whose potential is either a third potential of the selected word line or a fourth potential equal or lower than the first power supply is supplied to another source or drain of the P transistor.

摘要翻译： 本发明涉及一种设在存储器电路中的字驱动器电路。 字驱动器电路包括P沟道和N沟道晶体管，其具有共同连接的栅极电极和通常连接的一个源极或漏极电极。 N沟道晶体管具有连接到地的另一个源极或漏极。 字线连接到晶体管的共同连接的源极或漏极。 通过解码第一组地址信号而产生的第一选择信号被提供给栅极电极，该第一组地址信号的电位是N沟道晶体管导通的第一电位或低于第一电源的第二电位。 并且通过解码第二组地址信号而产生的第二选择信号被提供给P的另一个源或漏极，该第二组地址信号的电位是所选字线的第三电位或等于或低于第一电源的第四电位 晶体管。