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    Semiconductor integrated circuit device having fuse-type information storing circuit
    2.
    发明授权
    Semiconductor integrated circuit device having fuse-type information storing circuit 失效
    具有熔丝型信息存储电路的半导体集成电路装置

    公开(公告)号：US4707806A

    公开(公告)日：1987-11-17

    申请号：US712149

    申请日：1985-03-15

    申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Masao Nakano ,  Norihisa Tsuge, deceased

    发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Masao Nakano ,  Norihisa Tsuge, deceased

    IPC分类号： H01L27/00 ,  G11C8/10 ,  G11C17/14 ,  G11C17/16 ,  G11C29/00 ,  G11C29/04 ,  H01L23/525 ,  G11C11/00

    CPC分类号： G11C29/785 ,  G11C17/16 ,  G11C8/10 ,  H01L23/5256 ,  H01L2924/0002

    摘要： A device connected between first and second voltage feed lines includes an information storing circuit having a fuse for storing information by blowing or not blowing the fuse, a voltage level conversion circuit connected to at least one of the first and second voltage feed lines and outputting a voltage lower than a voltage between the first and second voltage feed lines to the information storing circuit, and a circuit connected between the first and second voltage feed lines, for outputting a detection signal in response to a voltage value at the fuse in the information storing circuit to which the voltage is applied from the voltage level conversion circuit and which voltage value is varied with the blown or unblown state of the fuse.In a normal operation, the voltage output from the voltage level conversion circuit can be set as low as possible to restrain electromigration caused at the vicinity of the blown portion of the fuse to which the voltage is applied, but higher than the threshold voltage of the information detection circuit.

    摘要翻译： 连接在第一和第二电压馈送线之间的装置包括信息存储电路，该信息存储电路具有熔丝，用于通过吹送或不熔断熔丝来存储信息;电压电平转换电路，连接到第一和第二电压馈送线中的至少一个并输出一个 电压低于第一和第二电压馈送线之间的电压到信息存储电路，以及电路，连接在第一和第二电压馈送线之间，用于响应于信息存储中的熔丝处的电压值输出检测信号 从电压电平转换电路向其施加电压的电路，以及哪个电压值随着保险丝的熔断或非吹出状态而变化。 在正常操作中，可以将从电压电平转换电路输出的电压设置得尽可能低以抑制在施加电压的熔丝的熔断部分附近引起的电迁移，但是高于 信息检测电路。

    Semiconductor integrated circuit
    4.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US4583179A

    公开(公告)日：1986-04-15

    申请号：US454254

    申请日：1982-12-29

    申请人： Takashi Horii ,  Tomio Nakano ,  Masao Nakano ,  Norihisa Tsuge ,  Junji Ogawa

    发明人： Takashi Horii ,  Tomio Nakano ,  Masao Nakano ,  Norihisa Tsuge ,  Junji Ogawa

    IPC分类号： H01L21/822 ,  G01R31/317 ,  G11C29/00 ,  G11C29/04 ,  H01L21/66 ,  H01L27/04 ,  G06F11/30 ,  G01R19/165 ,  G11C11/40

    CPC分类号： G11C29/835 ,  G01R31/31701

    摘要： A semiconductor integrated circuit which includes therein at least one inspection circuit for inspecting a voltage level produced at an internal node to be inspected. The inspection circuit has at least a control signal input portion connected to the internal node to be inspected and an input part connected to an external input/output pin. The inspection circuit includes a series-connected transistor and diode connected between a power source and the input portion, a capacitor connected between a gate of the transistor and the input portion, and a transfer gate transistor connected between the control signal input portion and the gate of the transistor. The inspection circuit discriminates the level at the internal node according to a flow or nonflow of a current, via the external input/output pin, when a particular signal having a voltage level higher than the power source level is supplied to the external input/output pin.

    摘要翻译： 一种半导体集成电路，其中包括至少一个检查电路，用于检查在待检查的内部节点处产生的电压电平。 检查电路至少具有连接到要检查的内部节点的控制信号输入部分和连接到外部输入/输出引脚的输入部分。 检查电路包括连接在电源和输入部分之间的串联晶体管和二极管，连接在晶体管的栅极和输入部分之间的电容器，以及连接在控制信号输入部分和栅极之间的传输栅极晶体管 的晶体管。 当具有高于电源电平的电压电平的特定信号被提供给外部输入/输出时，检查电路通过外部输入/输出引脚根据电流的流量或非流量来鉴别内部节点处的电平 销。

    MIS transistor circuit
    5.
    发明授权
    MIS transistor circuit 失效
    MIS晶体管电路

    公开(公告)号：US4578781A

    公开(公告)日：1986-03-25

    申请号：US413405

    申请日：1982-08-31

    申请人： Junji Ogawa ,  Tomio Nakano ,  Masao Nakano ,  Norihisa Tsuge ,  Takashi Horii

    发明人： Junji Ogawa ,  Tomio Nakano ,  Masao Nakano ,  Norihisa Tsuge ,  Takashi Horii

    IPC分类号： G11C29/02 ,  G11C5/14 ,  G11C11/407 ,  G11C11/4074 ,  H03K3/353 ,  G11C7/00

    CPC分类号： G11C5/145 ,  G11C11/4074

    摘要： An MIS transistor circuit which is operated alternately in a reset state and in an active state, comprises a voltage holding circuit for holding a power supply voltage applied in each reset state so as to provide a clamped voltage. The clamped voltage is applied during each active state to the desired nodes of the MIS transistor circuit as an actual power supply voltage, whereby error operation due to voltage fluctuation of the power supply voltage is prevented.

    摘要翻译： 在复位状态和活动状态下交替操作的MIS晶体管电路包括用于保持在每个复位状态下施加的电源电压以提供钳位电压的电压保持电路。 在每个激活状态期间将钳位电压施加到MIS晶体管电路的期望节点作为实际电源电压，从而防止由于电源电压的电压波动引起的误操作。

    Simultaneous dual access semiconductor memory device
    7.
    发明授权
    Simultaneous dual access semiconductor memory device 失效
    同时双接入半导体存储器件

    公开(公告)号：US4819209A

    公开(公告)日：1989-04-04

    申请号：US63989

    申请日：1987-06-19

    申请人： Yoshihiro Takemae ,  Takashi Horii

    发明人： Yoshihiro Takemae ,  Takashi Horii

    IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C8/12 ,  G11C11/408 ,  G11C11/4097 ,  G11C8/00 ,  G11C5/02 ,  G11C7/00

    CPC分类号： G11C8/12 ,  G11C11/408 ,  G11C11/4097 ,  G11C7/18

    摘要： A semiconductor memory device includes: a memory cell array constituted of a plurality of memory cell array units; transfer gates inserted in bit lines between the adjacent memory cell array units; a first and a second column decoders connected to both ends of bit lines in which the transfer gates are inserted; a row decoder connected to word lines of the memory cell array. The row decoder is adapted to be divided selectively in two parts; and two sets of row/column addresses are supplied to the column decoders and the row decoder. Therefore, simultaneous separate accesses to the memory cell array are carried out by the two sets of row/column addresses.

    摘要翻译： 半导体存储器件包括：由多个存储单元阵列单元构成的存储单元阵列; 插入在相邻存储单元阵列单元之间的位线中的传输门; 连接到所述传输门插入的位线的两端的第一和第二列解码器; 连接到存储单元阵列的字线的行解码器。 行解码器被选择性地分成两部分; 并且两列行/列地址被提供给列解码器和行解码器。 因此，通过两组行/列地址来执行对存储单元阵列的同时单独访问。

    Non-volatile memory having multiple erase operations
    9.
    发明授权
    Non-volatile memory having multiple erase operations 有权
    具有多次擦除操作的非易失性存储器

    公开(公告)号：US07581058B2

    公开(公告)日：2009-08-25

    申请号：US11963913

    申请日：2007-12-24

    申请人： Yoshinori Takase ,  Keiichi Yoshida ,  Takashi Horii ,  Atsushi Nozoe ,  Takayuki Tamura ,  Tomoyuki Fujisawa ,  Ken Matsubara

    发明人： Yoshinori Takase ,  Keiichi Yoshida ,  Takashi Horii ,  Atsushi Nozoe ,  Takayuki Tamura ,  Tomoyuki Fujisawa ,  Ken Matsubara

    IPC分类号： G06F12/06

    CPC分类号： G06F12/0246 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/7203 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/22

    摘要： A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.

    摘要翻译： 非易失性存储设备（1）具有非易失性存储单元（FARY0至FARY3），缓冲单元（BMRY0至BMRY3）和控制单元（CNT）），控制单元可以控制外部和 所述缓冲器单元以及当从所述外部分别接收到指令时，所述非易失性存储器单元和所述缓冲器单元之间的第二访问处理。 控制单元可以分别根据从外部发送的指令独立地对非易失性存储器单元和缓冲单元执行访问控制。 因此，可以与非易失性存储器单元的擦除操作同时地将缓冲单元的下一个写入数据设置为缓冲单元，或者按照高速缓存存储器操作中的高速将高速存储信息一次性地输出到缓冲器单元 指令从外面发出。 因此，可以减少用于从/向非易失性存储装置读/写数据的数据传输的开销。

    Variable venturi carburetor
    10.
    发明授权
    Variable venturi carburetor 失效
    可变文丘里化油器

    公开(公告)号：US4454076A

    公开(公告)日：1984-06-12

    申请号：US454577

    申请日：1982-12-30

    申请人： Satomi Wada ,  Masanori Senda ,  Takashi Horii ,  Yozo Ota

    发明人： Satomi Wada ,  Masanori Senda ,  Takashi Horii ,  Yozo Ota

    IPC分类号： F02M7/17 ,  F02M9/06

    CPC分类号： F02M7/17 ,  Y10S261/56

    摘要： Disclosed herein is a variable venturi carburetor including at least one pressure controlling port provided at the lower peripheral portion of the suction piston and adapted to face to a mixing chamber defined directly downstream of the venturi portion. The pressure controlling port is located at such a position as to communicate with the suction chamber and an atmospheric pressure chamber during middle and high intake air flowing stages as the suction piston reciprocates transversely with respect to the venturi portion, and to communicate with the suction chamber and the mixing chamber during low intake air flowing stage.

    摘要翻译： 本文公开了一种可变文丘里化油器，其包括设置在吸入活塞的下周边部分处的至少一个压力控制口，并且适于面向直接在文氏管部分下游限定的混合室。 压力控制口位于这样一个位置，当吸入活塞相对于文丘里管部分横向往复运动时，位于中空和高吸入气流阶段期间与抽吸室和大气压力室连通的位置，并与吸入室 以及在低进气流动阶段的混合室。