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1.发明申请FLASH A/D CONVERTER, FLASH A/D CONVERSION MODULE, AND DELTA-SIGMA A/D CONVERTER 审中-公开闪存A / D转换器，闪存A / D转换模块和DELTA-SIGMA A / D转换器公开(公告)号：US20110018752A1
公开(公告)日：2011-01-27
申请号：US12899154
申请日：2010-10-06
申请人： Masao TAKAYAMA , Kazuo Matsukawa , Yosuke Mitani , Shiro Dosho
发明人： Masao TAKAYAMA , Kazuo Matsukawa , Yosuke Mitani , Shiro Dosho
摘要： In a flash A/D converter, a predictor predicts next analog input data based on a digital output signal from an A/D converter, and outputs prediction data. Based on the prediction data from the predictor, a controller turns on comparators having reference voltages near the prediction data, and in order to ensure a certain degree of A/D conversion accuracy even when the prediction fails, also turns on even-numbered comparators 103.2a (where a is 0 to 7), for example. In this manner, even when prediction of next analog input data fails, a 4-bit A/D converter can perform A/D conversion with 3-bit accuracy, while saving power consumption by reducing the number of comparators to be turned on.
摘要翻译： 在闪存A / D转换器中，预测器基于来自A / D转换器的数字输出信号预测下一个模拟输入数据，并输出预测数据。 基于来自预测器的预测数据，控制器打开具有靠近预测数据的参考电压的比较器，并且即使在预测失败时也确保一定程度的A / D转换精度，也打开偶数比较器103.2 a（其中a为0至7）。 以这种方式，即使当下一个模拟输入数据的预测失败时，四位A / D转换器也可以以3位精度执行A / D转换，同时通过减少比较器的数量来导通，从而节省功耗。
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公开(公告)号：US20110050476A1
公开(公告)日：2011-03-03
申请号：US12888126
申请日：2010-09-22
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
摘要： An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n−1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n−1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.
摘要翻译： 积分器包括运算放大器，连接到运算放大器的反相输入端的第一滤波器和连接在运算放大器的反相输入端和输出端之间的第二滤波器。 第一滤波器包括串联连接的n个电阻元件和（n-1）个电容元件，每个电容元件的一端连接到电阻元件的互连节点，另一端连接到地。 第二滤波器包括串联连接的n个电容元件和（n-1）个电阻元件，每个电阻元件的一端连接到电容元件的互连节点，另一端连接到地。
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3.发明申请公开(公告)号：US20120262320A1
公开(公告)日：2012-10-18
申请号：US13534716
申请日：2012-06-27
申请人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
发明人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
CPC分类号： H03H11/04 , H03H2011/0488 , H03M3/404
摘要： Two T filters, one of which includes two resistive elements and one capacitive element and the other of which includes two capacitive elements and one resistive element, are inserted in a negative-feedback section of an operational amplifier, and a resistive element and a capacitive element are connected between each of intermediate nodes and a signal input terminal. A resistive element and a capacitive element which are connected to each other in parallel are connected between the signal input terminal and an inverting input terminal of the operational amplifier. With this configuration, overall admittances where elements connected to the corresponding intermediate nodes are in parallel connection are equal to each other.
摘要翻译： 两个T滤波器，其中一个包括两个电阻元件和一个电容元件，另一个包括两个电容元件和一个电阻元件，插入到运算放大器的负反馈部分中，电阻元件和电容元件 连接在每个中间节点和信号输入端子之间。 并联连接的电阻元件和电容元件连接在信号输入端子和运算放大器的反相输入端子之间。 利用这种配置，连接到对应的中间节点的元件并联连接的整体导纳彼此相等。
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公开(公告)号：US08823567B2
公开(公告)日：2014-09-02
申请号：US13534716
申请日：2012-06-27
申请人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
发明人： Yosuke Mitani , Kazuo Matsukawa , Masao Takayama , Koji Obata , Shiro Dosho
CPC分类号： H03H11/04 , H03H2011/0488 , H03M3/404
摘要： Two T filters, one of which includes two resistive elements and one capacitive element and the other of which includes two capacitive elements and one resistive element, are inserted in a negative-feedback section of an operational amplifier, and a resistive element and a capacitive element are connected between each of intermediate nodes and a signal input terminal. A resistive element and a capacitive element which are connected to each other in parallel are connected between the signal input terminal and an inverting input terminal of the operational amplifier. With this configuration, overall admittances where elements connected to the corresponding intermediate nodes are in parallel connection are equal to each other.
摘要翻译： 两个T滤波器，其中一个包括两个电阻元件和一个电容元件，另一个包括两个电容元件和一个电阻元件，插入到运算放大器的负反馈部分中，电阻元件和电容元件 连接在每个中间节点和信号输入端子之间。 并联连接的电阻元件和电容元件连接在信号输入端子和运算放大器的反相输入端子之间。 利用这种配置，连接到对应的中间节点的元件并联连接的整体导纳彼此相等。
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公开(公告)号：US20110200077A1
公开(公告)日：2011-08-18
申请号：US13094519
申请日：2011-04-26
申请人： Yosuke MITANI , Kazuo Matsukawa , Masao Takayama , Shiro Dosho
发明人： Yosuke MITANI , Kazuo Matsukawa , Masao Takayama , Shiro Dosho
摘要： In a DSM including a loop in which an output signal of a quantizer is digitally processed, and fed back through a DAC to an analog filter, the quantizer quantizes an analog signal from an analog filter section to output a digital signal. The digital signal from the quantizer is digitally processed in a first-order recursive filter circuit including a variable gain amplifier and a delay element. A LUT receives both the digital signal from the quantizer and a table control signal, which is an output signal from the recursive filter circuit, and stores in advance compensation values corresponding to the both signals. A compensation value from the LUT is used to provide a digital output signal compensated for a delay. The digital output signal is converted into an analog signal in the DAC, and then subtracted from an analog input signal in the analog filter section.
摘要翻译： 在包括量化器的输出信号被数字处理并通过DAC反馈到模拟滤波器的环路的DSM中，量化器对来自模拟滤波器部分的模拟信号进行量化以输出数字信号。 来自量化器的数字信号在包括可变增益放大器和延迟元件的一阶递归滤波器电路中进行数字处理。 LUT接收来自量化器的数字信号和作为来自递归滤波器电路的输出信号的表控制信号，并且预先存储对应于两个信号的补偿值。 来自LUT的补偿值用于提供补偿延迟的数字输出信号。 数字输出信号在DAC中转换为模拟信号，然后从模拟滤波器部分的模拟输入信号中减去。
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公开(公告)号：US20110133964A1
公开(公告)日：2011-06-09
申请号：US13025666
申请日：2011-02-11
申请人： Shiro DOSHO , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
发明人： Shiro DOSHO , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
摘要： An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.
摘要翻译： 过采样A / D转换器包括：第一滤波器，包括第一电阻元件，第一电容元件，第二电阻元件，运算放大器和第二电容元件; 接收第一滤波器的输出的第二滤波器; 第三滤波器，包括第三电阻元件，第三电容元件和第四电阻元件; 量化器，接收第三滤波器的输出并产生数字信号; 以及将数字信号转换成模拟电流信号的D / A转换器。 D / A转换器将产生的模拟电流信号输入到运算放大器的反相输入端。
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公开(公告)号：US08466820B2
公开(公告)日：2013-06-18
申请号：US13025666
申请日：2011-02-11
申请人： Shiro Dosho , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
发明人： Shiro Dosho , Kazuo Matsukawa , Masao Takayama , Yosuke Mitani
IPC分类号： H03M3/00
摘要： An oversampling A/D converter includes a first filter including a first resistive element, a first capacitive element, a second resistive element, an operational amplifier, and a second capacitive element; a second filter receiving an output of the first filter; a third filter including a third resistive element, a third capacitive element, and a fourth resistive element; a quantizer receiving an output of the third filter and generating a digital signal; and a D/A converter converting the digital signal to an analog current signal. The D/A converter inputs the generated analog current signal to an inverting input terminal of the operational amplifier.
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公开(公告)号：US08258990B2
公开(公告)日：2012-09-04
申请号：US12888126
申请日：2010-09-22
申请人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
发明人： Shiro Dosho , Takashi Morie , Kazuo Matsukawa , Yosuke Mitani , Masao Takayama
IPC分类号： H03M3/00
摘要： An integrator includes an operational amplifier, a first filter connected to an inverting input terminal of the operational amplifier, and a second filter connected between the inverting input terminal and an output terminal of the operational amplifier. The first filter includes n resistive elements connected in series, and (n−1) capacitive elements each having one end connected to an interconnecting node of the resistive elements and the other end connected to ground. The second filter includes n capacitive elements connected in series, and (n−1) resistive elements each having one end connected to an interconnecting node of the capacitive elements and the other end connected to ground.
摘要翻译： 积分器包括运算放大器，连接到运算放大器的反相输入端的第一滤波器和连接在运算放大器的反相输入端和输出端之间的第二滤波器。 第一滤波器包括串联连接的n个电阻元件和（n-1）个电容元件，每个电容元件的一端连接到电阻元件的互连节点，另一端连接到地。 第二滤波器包括串联连接的n个电容元件和（n-1）个电阻元件，每个电阻元件的一端连接到电容元件的互连节点，另一端连接到地。
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公开(公告)号：US20110169677A1
公开(公告)日：2011-07-14
申请号：US13073335
申请日：2011-03-28
申请人： Shiro DOSHO , Kazuo Matsukawa , Yosuke Mitani
发明人： Shiro DOSHO , Kazuo Matsukawa , Yosuke Mitani
CPC分类号： H03M3/454 , H03H11/1252 , H03M3/404 , H03M3/438
摘要： Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.
摘要翻译： 两个电阻元件和电容元件耦合在运算放大器的第一节点和反相输入端子，运算放大器的输出端子和公共节点之间。 电阻元件和电容元件耦合在第一节点和信号输入端子之间。 两个电容元件和电阻元件耦合在第二节点和反相输入端子，输出端子和公共节点之间。 两个电容元件耦合在第二节点和每个信号输入端和公共节点之间。
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公开(公告)号：US08604956B2
公开(公告)日：2013-12-10
申请号：US13073335
申请日：2011-03-28
申请人： Shiro Dosho , Kazuo Matsukawa , Yosuke Mitani
发明人： Shiro Dosho , Kazuo Matsukawa , Yosuke Mitani
IPC分类号： H03M3/00
CPC分类号： H03M3/454 , H03H11/1252 , H03M3/404 , H03M3/438
摘要： Two resistive elements and a capacitive element are coupled between a first node and each of an inverting input terminal of an operational amplifier, an output terminal of the operational amplifier, and a common node. A resistive element and a capacitive element are coupled between the first node and a signal input terminal. Two capacitive elements and a resistive element are coupled between a second node and each of the inverting input terminal, the output terminal, and the common node. Two capacitive elements are coupled between the second node and each of the signal input terminal, and the common node.
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