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13 条记录 (耗时 0.047 秒)

    Display apparatus and method thereof
    1.
    发明授权
    Display apparatus and method thereof 有权
    显示装置及其方法

    公开(公告)号：US08558780B2

    公开(公告)日：2013-10-15

    申请号：US12043396

    申请日：2008-03-06

    申请人： Young-A Lee ,  Yong-Hyun Hwang ,  Kwang-Soo Lee ,  Dong-Gyu Lee ,  Doo-Won Lee ,  Jong-Young Yun ,  Neung-Beom Lee

    发明人： Young-A Lee ,  Yong-Hyun Hwang ,  Kwang-Soo Lee ,  Dong-Gyu Lee ,  Doo-Won Lee ,  Jong-Young Yun ,  Neung-Beom Lee

    IPC分类号： G09G3/36

    CPC分类号： G09F9/35 ,  G09F13/04 ,  G09G3/3406 ,  G09G2300/02

    摘要： A display apparatus includes a backlight assembly, a first display panel assembly and a second display panel assembly. The backlight assembly includes a plurality of lamps disposed substantially parallel with each other. The backlight assembly emits first light through a first face and second light through a second face. The first display panel assembly is disposed adjacent to the first face to receive the first light. The second display panel assembly is disposed adjacent to the second face to receive the second light. The backlight assembly may further include a driving inverter electrically connected to first and second ends of the lamps to provide the lamps with driving voltages. Therefore, the backlight assembly applies light to the first and second display panel assemblies to reduce the number of backlight assemblies. Therefore, costs for manufacturing a display apparatus may be reduced.

    摘要翻译： 显示装置包括背光组件，第一显示面板组件和第二显示面板组件。 背光组件包括基本上彼此平行设置的多个灯。 背光组件通过第一面和第二光通过第二面发射第一光。 第一显示面板组件设置成与第一面相邻以接收第一光。 第二显示面板组件设置成与第二面相邻以接收第二光。 背光组件还可以包括电连接到灯的第一和第二端的驱动逆变器以向灯提供驱动电压。 因此，背光组件将光施加到第一和第二显示面板组件以减少背光组件的数量。 因此，可以降低制造显示装置的成本。

    Printed circuit board for a package and manufacturing method thereof
    2.
    发明申请
    Printed circuit board for a package and manufacturing method thereof 审中-公开
    一种封装用印刷电路板及其制造方法

    公开(公告)号：US20090205854A1

    公开(公告)日：2009-08-20

    申请号：US12219140

    申请日：2008-07-16

    申请人： Dong-Gyu Lee ,  Jin-Won Choi ,  Ki-Young Yoo ,  Tae-Joon Chung

    发明人： Dong-Gyu Lee ,  Jin-Won Choi ,  Ki-Young Yoo ,  Tae-Joon Chung

    IPC分类号： H05K1/09 ,  H05K3/00

    CPC分类号： H05K3/243 ,  H01L2224/16 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H05K1/0269 ,  H05K3/0035 ,  H05K3/244 ,  H05K3/282 ,  H05K3/3452 ,  H05K3/3473 ,  H05K2201/0391 ,  H05K2201/09918 ,  H05K2203/054 ,  Y10T29/49149 ,  H01L2924/00

    摘要： A printed circuit board for use in a package and to a method of manufacturing the printed circuit board. The method of manufacturing the printed circuit board can include: providing a substrate, on one side of which at least one solder pad and at least one guide pad are formed; forming a solder resist layer over the one side of the substrate; uncovering at least one portion of the solder resist layer such that the guide pad is exposed; applying a surface treatment on the exposed guide pad; uncovering at least one portion of the solder resist layer such that the solder pad is exposed; and forming a solder bump on the exposed solder pad. With this method, the amount of surface treatment applied can be minimized, for reduced costs, and the occurrence of undiffused layers can be avoided, for improved reliability in the final product.

    摘要翻译： 一种用于封装的印刷电路板和制造印刷电路板的方法。 制造印刷电路板的方法可以包括：提供衬底，在衬底的一侧上形成至少一个焊盘和至少一个引导垫; 在衬底的一侧上形成阻焊层; 露出阻焊层的至少一部分，使得引导垫暴露; 在暴露的导向垫上进行表面处理; 露出阻焊层的至少一部分，使焊料焊盘露出; 并在暴露的焊盘上形成焊料凸块。 通过这种方法，可以最小化施加的表面处理量，从而降低成本，并且可以避免出现未扩散的层，从而提高最终产品的可靠性。

    Dynamic programmable logic array having enable unit
    3.
    发明授权
    Dynamic programmable logic array having enable unit 失效
    动态可编程逻辑阵列具有使能单元

    公开(公告)号：US07245149B2

    公开(公告)日：2007-07-17

    申请号：US11102161

    申请日：2005-04-08

    申请人： Dong-Gyu Lee

    发明人： Dong-Gyu Lee

    IPC分类号： G06F7/38

    CPC分类号： H03K19/17712 ,  H03K19/1772

    摘要： A DPLA (dynamic programmable logic array) uses an enable unit for each output line that provides OR-functionality, to eliminate a clock signal in the OR-plane. A clock signal is used only in the AND-plane for pre-charging the product term lines. Such a DPLA operates properly without a delay constraint between clock signals in both the AND-plane and the OR-plane for proper operation at higher frequencies.

    摘要翻译： DPLA（动态可编程逻辑阵列）为提供OR功能的每个输出线使用使能单元，以消除OR平面中的时钟信号。 时钟信号仅在AND平面中用于对产品项线进行预充电。 这样的DPLA在AND平面和OR平面中的时钟信号之间没有延迟约束的情况下正常工作，以在较高频率下正常工作。

    Programmable logic array
    4.
    发明申请
    Programmable logic array 失效

    公开(公告)号：US20060125519A1

    公开(公告)日：2006-06-15

    申请号：US11295634

    申请日：2005-12-07

    申请人： Dong-Gyu Lee

    发明人： Dong-Gyu Lee

    IPC分类号： H03K19/177

    CPC分类号： H03K19/1772

    摘要： A programmable logic array (PLA) which may include an AND-plane receiving first input signals and generating logic product signals based on the first input signals, and an OR-plane receiving the logic product signals and a second input signal and generating a logic sum signal based on the logic product signals.

    Dynamic programmable logic array having enable unit
    5.
    发明申请
    Dynamic programmable logic array having enable unit 失效
    动态可编程逻辑阵列具有使能单元

    公开(公告)号：US20050264317A1

    公开(公告)日：2005-12-01

    申请号：US11102161

    申请日：2005-04-08

    申请人： Dong-Gyu Lee

    发明人： Dong-Gyu Lee

    IPC分类号： G06F9/22 ,  H03K19/00 ,  H03K19/177

    CPC分类号： H03K19/17712 ,  H03K19/1772

    摘要： A DPLA (dynamic programmable logic array) uses an enable unit for each output line that provides OR-functionality, to eliminate a clock signal in the OR-plane. A clock signal is used only in the AND-plane for pre-charging the product term lines. Such a DPLA operates properly without a delay constraint between clock signals in both the AND-plane and the OR-plane for proper operation at higher frequencies.

    摘要翻译： DPLA（动态可编程逻辑阵列）为提供OR功能的每个输出线使用使能单元，以消除OR平面中的时钟信号。 时钟信号仅在AND平面中用于对产品项线进行预充电。 这样的DPLA在AND平面和OR平面中的时钟信号之间没有延迟约束的情况下正常工作，以在较高频率下正常工作。

    Apparatus and method for calculation of divisions and square roots
    9.
    发明申请
    Apparatus and method for calculation of divisions and square roots 有权

    公开(公告)号：US20070118584A1

    公开(公告)日：2007-05-24

    申请号：US11654255

    申请日：2007-01-17

    申请人： Dong-Gyu Lee

    发明人： Dong-Gyu Lee

    IPC分类号： G06F7/44

    CPC分类号： G06F7/535 ,  G06F7/483 ,  G06F7/4873 ,  G06F7/5375 ,  G06F7/5525 ,  G06F2207/5528

    摘要： Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {−1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial remainder from (i−2)'th iterative operation and by the quotient/root prediction table. The present procedures generate the (i−1)'th correction term, which is to be applied in calculating the i'th partial remainder, simultaneously with the (i−2)'th correction term, and need not to perform an iterative operation to obtain the i'th partial remainder.

    Apparatus and method for calculation of divisions and square roots
    10.
    发明授权
    Apparatus and method for calculation of divisions and square roots 失效
    用于计算分割和平方根的装置和方法

    公开(公告)号：US07185040B2

    公开(公告)日：2007-02-27

    申请号：US10262449

    申请日：2002-10-01

    申请人： Dong-Gyu Lee

    发明人： Dong-Gyu Lee

    IPC分类号： G06F7/38

    CPC分类号： G06F7/535 ,  G06F7/483 ,  G06F7/4873 ,  G06F7/5375 ,  G06F7/5525 ,  G06F2207/5528

    摘要： Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {−1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial remainder from (i−2)'th iterative operation and by the quotient/root prediction table. The present procedures generate the (i−1)'th correction term, which is to be applied in calculating the i'th partial remainder, simultaneously with the (i−2)'th correction term, and need not to perform an iterative operation to obtain the i'th partial remainder.

    摘要翻译： 提供了非恢复基数2和平方根生成程序。 所提出的程序利用商/根数字集{-1,0，+1}和商/根预测表（QRT / RPT）。 参照第（i-2）'次迭代运算和商/根预测表的部分余数来确定第i个商/根数。 本步骤生成与第（i-2）个校正项同时计算第i个部分余数时应用的第（i-1）个校正项，并且不需要执行迭代操作 以获得第i个部分余数。