公开(公告)号：US20060281289A1

公开(公告)日：2006-12-14

申请号：US11446981

申请日：2006-06-06

申请人： Young-Cheon Kim ,  Chul Hwangbo ,  Rak-Hwan Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

发明人： Young-Cheon Kim ,  Chul Hwangbo ,  Rak-Hwan Kim ,  Hyeon-Deok Lee ,  In-Sun Park ,  Ji-Soon Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/26513 ,  H01L21/28061 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4933 ,  H01L29/6659 ,  H01L29/7833

摘要： In a method of forming a polycide layer and method of manufacturing a semiconductor device having the polycide layer, the method may include forming a preliminary polysilicon layer doped with first type impurities on a substrate having a first region and a second region, implanting second type of impurities into a portion of the preliminary polysilicon layer on the second region, heat treating the preliminary polysilicon layer to electrically activate the impurities, removing a portion of an upper surface of the heat treated preliminary polysilicon layer to obtain a polysilicon layer, forming a metal silicide layer on the polysilicon layer, and patterning the polysilicon layer and the metal silicide layer to form a first type gate electrode on the first region and to form a second type gate electrode on the second region.

摘要翻译： 在形成多晶硅化合物层的方法和制造具有多晶硅化物层的半导体器件的方法中，该方法可以包括在具有第一区域和第二区域的衬底上形成掺杂有第一类型杂质的初步多晶硅层， 杂质进入第二区域的初步多晶硅层的一部分，热处理初步多晶硅层以电激活杂质，去除热处理的初步多晶硅层的上表面的一部分以获得多晶硅层，形成金属硅化物 并且在所述第一区域上形成所述多晶硅层和所述金属硅化物层以形成第一类型的栅电极，并在所述第二区域上形成第二类型的栅电极。

公开(公告)号：US07504725B2

公开(公告)日：2009-03-17

申请号：US10915871

申请日：2004-08-09

申请人： Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

发明人： Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/28556 ,  H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76876 ,  H01L27/10885 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device and a method of manufacturing the semiconductor memory device, in which a bit line can have a low resistance without an increase in the thickness of the bit line. In the semiconductor memory device, an insulating layer having a contact hole that exposes a conductive region is formed on a semiconductor substrate having the conductive region. A barrier metal layer is formed along the surface of the insulating layer and the surface of the contact hole. A grain control layer is formed between the barrier metal layer and the tungsten layer. A tungsten layer is formed on the grain control layer. A grain size of the tungsten layer is increased by the grain control layer.

摘要翻译： 一种半导体存储器件和半导体存储器件的制造方法，其中位线可以具有低电阻而不增加位线的厚度。 在半导体存储器件中，在具有导电区域的半导体衬底上形成具有暴露导电区域的接触孔的绝缘层。 沿着绝缘层的表面和接触孔的表面形成阻挡金属层。 在阻挡金属层与钨层之间形成晶粒控制层。 在晶粒控制层上形成钨层。 钨层的晶粒尺寸由晶粒控制层增加。

公开(公告)号：US20050042829A1

公开(公告)日：2005-02-24

申请号：US10915871

申请日：2004-08-09

申请人： Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

发明人： Rak-Hwan Kim ,  Young-Cheon Kim ,  Hyeon-Deok Lee ,  Hyun-Young Kim ,  In-Sun Park

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485

CPC分类号： H01L23/485 ,  H01L21/28556 ,  H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76862 ,  H01L21/76876 ,  H01L27/10885 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device and a method of manufacturing the semiconductor memory device, in which a bit line can have a low resistance without an increase in the thickness of the bit line. In the semiconductor memory device, an insulating layer having a contact hole that exposes a conductive region is formed on a semiconductor substrate having the conductive region. A barrier metal layer is formed along the surface of the insulating layer and the surface of the contact hole. A grain control layer is formed between the barrier metal layer and the tungsten layer. A tungsten layer is formed on the grain control layer. A grain size of the tungsten layer is increased by the grain control layer.

摘要翻译： 一种半导体存储器件和半导体存储器件的制造方法，其中位线可以具有低电阻而不增加位线的厚度。 在半导体存储器件中，在具有导电区域的半导体衬底上形成具有暴露导电区域的接触孔的绝缘层。 沿着绝缘层的表面和接触孔的表面形成阻挡金属层。 在阻挡金属层与钨层之间形成晶粒控制层。 在晶粒控制层上形成钨层。 钨层的晶粒尺寸由晶粒控制层增加。

公开(公告)号：US06623798B2

公开(公告)日：2003-09-23

申请号：US09884993

申请日：2001-06-21

申请人： Ju-Cheol Shin ,  In-Sun Park ,  Young-Cheon Kim ,  Chul Whang-Bo ,  Hyeon-Deok Lee

发明人： Ju-Cheol Shin ,  In-Sun Park ,  Young-Cheon Kim ,  Chul Whang-Bo ,  Hyeon-Deok Lee

IPC分类号： C23C1642

CPC分类号： C23C16/4412 ,  C23C16/42 ,  C23C16/54

摘要： A chemical vapor deposition (CVD) method for depositing a suicide and a CVD system for performing the same are disclosed. A silicide is deposited on a substrate. Residual gases remaining from the depositing step are purged out by flowing air including H2O (g), to substantially remove fumes caused by the residual gases. In the purge step, the cycle purge is carried out at the conditions similar to the flow of atmosphere, to substantially remove the fumes.

公开(公告)号：US20070026671A1

公开(公告)日：2007-02-01

申请号：US11476793

申请日：2006-06-29

申请人： Rak-Hwan Kim ,  Young-Cheon Kim

发明人： Rak-Hwan Kim ,  Young-Cheon Kim

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76865 ,  H01L21/76843 ,  H01L21/76877

摘要： Provided is a method for forming low resistance metal films in which an underlying film, for example, a barrier layer or an adhesion layer, is formed on a semiconductor substrate. The underlying film is then subjected to a partial etch back in order to reduce the surface roughness and form a deposition surface. A metal film, for example, a tungsten film, is then formed on a deposition surface that has been formed on the underlying film. Forming the metal film on the deposition surface that has reduced surface roughness will tend to produce a metal film having a larger average grain size and, consequently, a lower sheet resistivity for a given film thickness.

摘要翻译： 提供一种形成低电阻金属膜的方法，其中在半导体衬底上形成底层膜，例如阻挡层或粘附层。 然后对底层膜进行部分回蚀，以减少表面粗糙度并形成沉积表面。 然后在已经形成在下面的膜上的沉积表面上形成金属膜，例如钨膜。 在沉积表面上形成具有降低的表面粗糙度的金属膜将倾向于产生具有较大平均晶粒尺寸的金属膜，并因此产生给定膜厚度的较低的薄层电阻率。

公开(公告)号：US06797575B2

公开(公告)日：2004-09-28

申请号：US10101209

申请日：2002-03-20

申请人： Young-Cheon Kim ,  In-Sun Park ,  Ju-Cheol Shin

发明人： Young-Cheon Kim ,  In-Sun Park ,  Ju-Cheol Shin

IPC分类号： H01L21336

CPC分类号： H01L21/32053

摘要： A method for preventing void formation in a polycide structure includes sequentially depositing a gate oxide film, a polysilicon film doped with impurities, a seed film having a sufficient amount of silicon for reacting with an overlaying tungsten layer, a tungsten silicide precursor layer; and an etch mask made of an insulating material on a semiconductor substrate; performing a patterned etching using the etch mask; and heat-treating the resulting structure in an oxygen atmosphere at an elevated temperature and pressure to form a polycide structure wherein void formation is prevented. Since the seed film has a sufficient amount of amorphous silicon for reacting to the tungsten, migration of silicon atoms to the interfacial surface between the polysilicon film and the tungsten silicide precursor layer is prevented, thereby preventing the formation of voids in the polysilicon film.

摘要翻译： 防止多晶硅结构中的空隙形成的方法包括依次沉积栅极氧化膜，掺杂杂质的多晶硅膜，具有足够量硅的种子膜以与覆盖钨层反应，硅化钨前体层; 以及由半导体衬底上的绝缘材料制成的蚀刻掩模; 使用所述蚀刻掩模进行图案化蚀刻; 并在氧气氛中在升高的温度和压力下对所得结构进行热处理，以形成防止空隙形成的多晶硅结构。 由于种子膜具有足够量的用于与钨反应的非晶硅，所以可防止硅原子迁移到多晶硅膜与硅化钨前体层之间的界面，从而防止在多晶硅膜中形成空隙。

公开(公告)号：US06451691B2

公开(公告)日：2002-09-17

申请号：US09794616

申请日：2001-02-28

申请人： Won-Sang Song ,  In-Sun Park ,  Kyung-Bum Koo ,  Young-Cheon Kim

发明人： Won-Sang Song ,  In-Sun Park ,  Kyung-Bum Koo ,  Young-Cheon Kim

IPC分类号： H01L2144

CPC分类号： H01L21/76885 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76867

摘要： A method of manufacturing a metal pattern of a semiconductor device. A Ti layer and a metal layer are successively formed on a semiconductor substrate or on an insulating layer. Then, a wiring pattern including a Ti layer pattern and a metal layer pattern is formed by patterning said Ti layer and the metal layer. Heat treating is employed under an atmosphere of a compound including nitrogen in order to react an exposed portion of the Ti layer pattern to form TiN as a main product, thereby increasing the stability and adhesiveness of the metal layer for subsequent processes.

摘要翻译： 一种制造半导体器件的金属图案的方法。 在半导体衬底或绝缘层上依次形成Ti层和金属层。 然后，通过图案化所述Ti层和金属层来形成包括Ti层图案和金属层图案的布线图案。 在包括氮的化合物的气氛下进行热处理，以使Ti层图案的暴露部分反应形成TiN作为主要产物，从而提高后续工艺中金属层的稳定性和粘附性。