公开(公告)号：US5723371A

公开(公告)日：1998-03-03

申请号：US517878

申请日：1995-08-23

申请人： Young-Kap Seo ,  Chi-Woo Kim ,  Ho-Chul Kang

发明人： Young-Kap Seo ,  Chi-Woo Kim ,  Ho-Chul Kang

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L29/786 ,  H01L21/84

CPC分类号： H01L29/66765 ,  H01L21/31138 ,  H01L21/32135 ,  H01L29/78669 ,  Y10S438/906 ,  Y10S438/978

摘要： A method for fabricating a thin film transistor having a taper-etched semiconductor film includes the steps of forming a gate electrode on a bare substrate; forming an insulating film on the gate electrode;p forming a semiconductor film by forming an amorphous silicon film layer on the insulating film and forming an N.sup.+ amorphous silicon film on the amorphous silicon film layer, descumming photoresist residue from the semiconductor film by using a specified gas and taper etching a part of the semiconductor film, which is uncoated with the photoresist, by using HCl and SF.sub.6, to form a gentle slope in the etching profile resulting from overetching.

摘要翻译： 一种用于制造具有锥形蚀刻半导体膜的薄膜晶体管的方法包括在裸衬底上形成栅电极的步骤; 在所述栅电极上形成绝缘膜; p通过在所述绝缘膜上形成非晶硅膜层而形成半导体膜，并在所述非晶硅膜层上形成N +非晶硅膜，通过使用规定的所述半导体膜从所述半导体膜除去光刻胶残渣 气体和锥度蚀刻通过使用HCl和SF6在光刻胶中未涂覆的半导体膜的一部分，以在由过蚀刻产生的蚀刻轮廓中形成平缓的斜率。

公开(公告)号：US07688292B2

公开(公告)日：2010-03-30

申请号：US11373671

申请日：2006-03-09

申请人： Kee-Chan Park ,  Ho-Suk Maeng ,  Seong-Il Park ,  Cheol-Min Kim ,  Chi-Woo Kim ,  Soong-Yong Joo ,  Il-Gon Kim

发明人： Kee-Chan Park ,  Ho-Suk Maeng ,  Seong-Il Park ,  Cheol-Min Kim ,  Chi-Woo Kim ,  Soong-Yong Joo ,  Il-Gon Kim

IPC分类号： G09G3/32

CPC分类号： G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2320/043

摘要： A display device includes a plurality of pixels, wherein each pixel includes: a light emitting element; a first capacitor connected between a first node and a second node; a driving transistor having an input terminal, an output terminal, and a control terminal connected to the second node where the driving transistor supplies a driving current to the light emitting element to emit light; a first switching unit supplying a first reference voltage to the driving transistor according to a first scanning signal and connecting the first node to a data voltage or the driving transistor; and a second switching unit supplying a driving voltage to the driving transistor according to a second scanning signal and connecting the first node to the data voltage. Accordingly, variations in threshold voltage of the driving transistor can be compensated for so that it is possible to display a uniform image.

摘要翻译： 显示装置包括多个像素，其中每个像素包括：发光元件; 连接在第一节点和第二节点之间的第一电容器; 驱动晶体管，其具有输入端子，输出端子和连接到所述第二节点的控制端子，其中所述驱动晶体管向所述发光元件提供驱动电流以发光; 第一开关单元，根据第一扫描信号向驱动晶体管提供第一参考电压，并将第一节点连接到数据电压或驱动晶体管; 以及第二开关单元，其根据第二扫描信号向驱动晶体管提供驱动电压，并将第一节点连接到数据电压。 因此，可以补偿驱动晶体管的阈值电压的变化，使得可以显示均匀的图像。

公开(公告)号：US20080026500A1

公开(公告)日：2008-01-31

申请号：US11781518

申请日：2007-07-23

申请人： Han-Na Jo ,  Chi-Woo Kim ,  Young-Jin Chang ,  Jae-Beom Choi

发明人： Han-Na Jo ,  Chi-Woo Kim ,  Young-Jin Chang ,  Jae-Beom Choi

IPC分类号： H01L33/00 ,  H01L21/335

CPC分类号： H01L27/1285

摘要： A flat panel display device includes a substrate including a pixel area having a plurality of pixel parts and a peripheral circuit area disposed adjacent to the pixel area to drive the pixel parts, a circuit TFT disposed in the peripheral circuit area, the circuit TFT including a first semiconductor layer having a first crystal growth in a lateral direction, and a pixel TFT disposed in the pixel area, the pixel TFT including a second semiconductor layer having a second crystal isotropic growth.

摘要翻译： 平板显示装置包括：基板，包括具有多个像素部分的像素区域和与像素区域相邻设置的外围电路区域以驱动像素部分;电路TFT，设置在外围电路区域中;电路TFT包括： 在横向方向上具有第一晶体生长的第一半导体层和设置在像素区域中的像素TFT，所述像素TFT包括具有第二晶体各向同性生长的第二半导体层。

公开(公告)号：US20060228908A1

公开(公告)日：2006-10-12

申请号：US11234609

申请日：2005-09-23

申请人： Se-Jin Chung ,  Chi-Woo Kim ,  Ui-Jin Chung ,  Dong-Byum Kim

发明人： Se-Jin Chung ,  Chi-Woo Kim ,  Ui-Jin Chung ,  Dong-Byum Kim

IPC分类号： H01L21/00

CPC分类号： H01L21/02686 ,  H01L21/02532 ,  H01L21/02691 ,  H01L21/2026 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78606 ,  H01L29/78675

摘要： In a method of manufacturing a polysilicon thin film and a method of manufacturing a TFT having the thin film, a laser beam is irradiated on a portion of an amorphous silicon thin film to liquefy the portion of the amorphous silicon thin film. The amorphous silicon thin film is on a first end portion of a substrate. The liquefied silicon is crystallized to form silicon grains. The laser beam is shifted from the first end portion towards a second end portion of the substrate opposite the first end portion by an interval in a first direction. The laser beam is then irradiated onto a portion of the amorphous silicon thin film adjacent to the silicon grains to form a first polysilicon thin film. Therefore, electrical characteristics of the amorphous silicon thin film may be improved.

公开(公告)号：US06337520B1

公开(公告)日：2002-01-08

申请号：US09031486

申请日：1998-02-26

申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Chun-Gi You

发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Chun-Gi You

IPC分类号： H01L2348

CPC分类号： G02F1/1368 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： The Mo or MoW composition layer has the low resistivity less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy etchant or a Cr etchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor device along with an Al layer and a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using a polymer layer, an etch gas system CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched by using the Mo or MoW layer as a mask, to use an etch gas system such as hydrogen halide and at least one selected from CF4, CHF3, CHClF2, CH3F and C2F6 yield the good characteristics of TFT, and H2 plasma treatment can cause the characteristics of the TFT to be improved.

摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金蚀刻剂或Cr蚀刻剂蚀刻以具有平滑的锥角，并且Mo或MoW层用于显示器或半导体的布线 装置以及Al层和Cr层。 由于可以通过调整沉积压力来沉积Mo或MoW层以对基底施加低应力，所以可以单个MoW层自身用作布线。 当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，蚀刻气体系统CF4 + O2可以防止Mo或MoW合金层的蚀刻，并且蚀刻气体SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。 此外，当通过使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用蚀刻气体系统如卤化氢和选自CF 4，CHF 3，CHClF 2，CH 3 F 和C2F6产生TFT的良好特性，并且H2等离子体处理可以导致TFT的特性得到改善。

公开(公告)号：US20120146978A1

公开(公告)日：2012-06-14

申请号：US13155779

申请日：2011-06-08

申请人： Jin-Woo Park ,  Seung-Kyu Lee ,  Chul-Ho Kim ,  Dong-Hoon Lee ,  Chi-Woo Kim

发明人： Jin-Woo Park ,  Seung-Kyu Lee ,  Chul-Ho Kim ,  Dong-Hoon Lee ,  Chi-Woo Kim

IPC分类号： G06F3/038 ,  G11C19/00

CPC分类号： G11C19/287

摘要： A shift register including a plurality of stages, each of them including a first node, a second node, and a third node being in a high-impedance state when the first node is in a high-impedance state. The shift register includes an input circuit unit inputting a driving voltage to the first node in response to an output signal of a previous stage, a driving circuit unit generating an output signal according to a voltage of the first node, and a holding unit holding the output signal at a level of a gate-off voltage according to a voltage of the second node in an inactive period of a current stage, in which the holding unit comprises a first diode which applies a clock signal to the second node.

摘要翻译： 一种移位寄存器，包括多个级，每个级包括第一节点，第二节点和第三节点，当第一节点处于高阻抗状态时处于高阻抗状态。 移位寄存器包括输入电路单元，其响应于前一级的输出信号向第一节点输入驱动电压，驱动电路单元根据第一节点的电压产生输出信号，以及保持单元， 输出信号在当前级的无效时段期间根据第二节点的电压的栅极截止电压的电平，其中保持单元包括向第二节点施加时钟信号的第一二极管。

公开(公告)号：US20120127148A1

公开(公告)日：2012-05-24

申请号：US13283409

申请日：2011-10-27

申请人： Seong-Jun Lee ,  Jin-Oh Park ,  Mu-Kyung Jeon ,  Yong-Kyu Jang ,  Dong-Hoon Lee ,  Chi-Woo Kim

发明人： Seong-Jun Lee ,  Jin-Oh Park ,  Mu-Kyung Jeon ,  Yong-Kyu Jang ,  Dong-Hoon Lee ,  Chi-Woo Kim

IPC分类号： G06F3/038 ,  G09G3/36

CPC分类号： G02F1/134363 ,  G02F1/136286 ,  G02F2001/134318 ,  G02F2001/134372 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0447 ,  G09G2320/0276 ,  G09G2320/0673

摘要： A display substrate includes an insulating substrate, a first gate line, a first lower electrode, a second lower electrode, a first upper electrode, and a second upper electrode. The insulating substrate includes a first pixel region and a second pixel region located at a first direction from the first pixel region. The first gate line extends in a second direction crossing the first direction on the insulating substrate. The first and the second lower electrodes are in the first and the second pixel regions, respectively. The first upper electrode overlaps the first lower electrode in the first pixel region and includes a first slit pattern extending in a third direction different from the first and the second directions. The second upper electrode overlaps the second lower electrode in the second pixel region and includes a second slit pattern extending in a fourth direction different from the first to third directions.

摘要翻译： 显示基板包括绝缘基板，第一栅极线，第一下部电极，第二下部电极，第一上部电极和第二上部电极。 绝缘基板包括位于距第一像素区域的第一方向的第一像素区域和第二像素区域。 第一栅极线在与绝缘基板上的第一方向交叉的第二方向上延伸。 第一和第二下部电极分别位于第一和第二像素区域中。 第一上电极与第一像素区域中的第一下电极重叠，并且包括沿与第一和第二方向不同的第三方向延伸的第一狭缝图案。 第二上电极与第二像素区域中的第二下电极重叠，并且包括沿与第一至第三方向不同的第四方向延伸的第二狭缝图案。

公开(公告)号：US07288442B2

公开(公告)日：2007-10-30

申请号：US10634867

申请日：2003-08-06

申请人： Hyang-Shik Kong ,  Myung-Koo Hur ,  Chi-Woo Kim

发明人： Hyang-Shik Kong ,  Myung-Koo Hur ,  Chi-Woo Kim

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： G02F1/13439 ,  G02F1/13458 ,  H01L21/76801 ,  H01L21/76838 ,  H01L23/53209 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/458 ,  H01L2924/0002 ,  H01L2924/00

摘要： First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.

摘要翻译： 首先，将铝基材料的导电材料沉积并图案化以形成包括栅极线，栅极焊盘和栅电极的栅极线。 通过在大于300℃的范围内沉积氮化硅5分钟形成栅极绝缘层，并依次形成半导体层和欧姆接触层。 接下来，沉积并图案化诸如Cr的金属的导体层以形成数据线，其包括与栅极线相交的数据线，源电极，漏电极和数据焊盘。 然后，沉积并图案化钝化层以形成暴露漏电极，栅极焊盘和数据焊盘的接触孔。 接下来，沉积并图案化氧化铟锌以形成分别连接到漏电极，栅极焊盘和数据焊盘的像素电极，冗余栅极焊盘和冗余数据焊盘。

公开(公告)号：US20070229747A1

公开(公告)日：2007-10-04

申请号：US11743378

申请日：2007-05-02

申请人： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

发明人： Woo-Suk Chung ,  Chi-Woo Kim ,  Bo-Young An ,  Hyong-Gon Lee ,  Sung-Hee Cho

IPC分类号： G02F1/1343

CPC分类号： G02F1/133512 ,  G02F1/134336 ,  G02F1/1345 ,  G02F2001/133337 ,  G02F2001/133388 ,  G02F2001/133397 ,  G09G3/3648 ,  G09G2330/08 ,  G09G2330/10

摘要： In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrode, and an image defect area caused by the impurity ions is screened with the black matrix.

摘要翻译： 在液晶显示器中，多个栅极线和数据线设置在包括显示区域作为屏幕的第一基板上，以及在显示区域外部的外围区域，其中多个像素电极电连接到栅极线 和数据线，并且一些像素电极延伸到位于周边区域中; 并且可选地，在与第一基板相对设置的第二基板上形成黑矩阵，用于屏蔽位于周边区域中的像素电极的延伸部分，在第一和第二基板上形成定向膜的摩擦方向朝向 位于外围区域的像素电极的延伸部分，使得取向膜表面上的杂质离子沿着摩擦方向行进，以在像素电极的延伸部分停止，并且屏蔽由杂质离子引起的图像缺陷区域 与黑色矩阵。

公开(公告)号：US06445004B1

公开(公告)日：2002-09-03

申请号：US09617311

申请日：2000-07-14

申请人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

发明人： Chang-Oh Jeong ,  Yang-Sun Kim ,  Myung-Koo Hur ,  Young-Jae Tak ,  Mun-Pyo Hong ,  Chi-Woo Kim ,  Jang-Soo Kim ,  Chun-Gi You

IPC分类号： H01L2904

CPC分类号： G02F1/136286 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13629 ,  H01L21/28008 ,  H01L23/4827 ,  H01L29/42384 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/00

摘要： The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl(+He) or SF6+Cl2(+He) can form the edge profile of contact holes to be smoothed. Also, when an amorphous silicon layer formed under the Mo or MoW layer is etched using the Mo or MoW layer as a mask, using an etch gas system that employs a gas such as hydrogen halide and at least one gas selected from CF4, CHF3, CHClF2, CH3F, and C2F6, yields good TFT characteristics, and H2 plasma treatment can further improve the TFT characteristics.

摘要翻译： Mo或MoW组合物层具有小于15μOMEGAcm的低电阻率，并且使用Al合金附魔或Cr附魔被蚀刻成具有平滑的锥角，并且Mo或MoW层用于显示器或 半导体显示器以及Al层或Cr层。 由于通过调节沉积压力可以沉积Mo或MoW层以便对基底施加低应力，所以可以单独使用单个MoW层作为布线。 当在钝化层或栅极绝缘层中形成接触孔时，通过使用聚合物层减少横向蚀刻，使用CF 4 + O 2的蚀刻气体系统可以防止Mo或MoW合金层的蚀刻，以及蚀刻气体 SF6 + HCl（+ He）或SF6 + Cl2（+ He）可以形成要平滑的接触孔的边缘轮廓。 此外，当使用Mo或MoW层作为掩模蚀刻形成在Mo或MoW层下面的非晶硅层时，使用采用诸如卤化氢和至少一种选自CF 4，CHF 3的气体的气体的蚀刻气体系统， CHClF 2，CH 3 F和C 2 F 6，产生良好的TFT特性，并且H 2等离子体处理可以进一步提高TFT特性。