公开(公告)号：US10169042B2

公开(公告)日：2019-01-01

申请号：US14852774

申请日：2015-09-14

申请人： Young-soo Sohn ,  Sei-jin Kim ,  Kwang-il Park ,  Tae-young Kim ,  Chul-woo Park

发明人： Young-soo Sohn ,  Sei-jin Kim ,  Kwang-il Park ,  Tae-young Kim ,  Chul-woo Park

IPC分类号： G06F12/00 ,  G06F9/30 ,  G06F15/78

摘要： A memory device performing an internal copy operation is provided. The memory device may receive a source address, a destination address, and page size information together with an internal copy command, compares the source address with the destination address, and performs an internal copy operation. The internal copy operation may be an internal block copy operation, an inter-bank copy operation, or an internal bank copy operation. The internal copy operation may be performed with respect to one-page data, half-page data, or quarter-page data, based on the page size information. The memory device may output as a flag signal a copy-done signal indicating that the internal copy operation has been completed.

公开(公告)号：US09627015B2

公开(公告)日：2017-04-18

申请号：US14852890

申请日：2015-09-14

申请人： Young-soo Sohn ,  Kwang-il Park ,  Sei-jin Kim ,  Tae-young Kim

发明人： Young-soo Sohn ,  Kwang-il Park ,  Sei-jin Kim ,  Tae-young Kim

IPC分类号： G11C7/00 ,  G11C7/10

CPC分类号： G11C7/109 ,  G11C7/1063 ,  G11C2207/2272

摘要： A memory device, system, and/or method are provided for performing a page state informing function. The memory device may compare one or more row addresses received along with a command, determine the page open/close state according to a page hit or miss generated as a result of comparison, count read or write commands with respect to pages corresponding to a same row address, and determine the page open/close state according to a read or write command number generated as a result of counting. The memory device may determine a page open/close state with respect to a corresponding page based on a page hit/miss and a read or write command number and output a flag signal. The memory device may provide the page open/close state for each channel. A memory controller may establish different page open/close policies for each channel.

公开(公告)号：US20140317469A1

公开(公告)日：2014-10-23

申请号：US14208795

申请日：2014-03-13

申请人： Young-soo Sohn ,  Kwang-il Park ,  Chul-woo Park ,  Jong-pil Son ,  Jae-youn Youn ,  Hoi-ju Chung

发明人： Young-soo Sohn ,  Kwang-il Park ,  Chul-woo Park ,  Jong-pil Son ,  Jae-youn Youn ,  Hoi-ju Chung

IPC分类号： G06F11/10 ,  G11C29/10

CPC分类号： G06F11/1068 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1052 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/808 ,  G11C29/848 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/1208

摘要： Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.

摘要翻译： 提供了执行ECC操作和冗余修复操作的存储器件和存储器模块。 存储器件通过使用纠错码（ECC）操作来修复由于“故障”单元而导致的单位错误，并且当“失败”单元不可修复时，通过使用冗余修复操作来修复“失败”单元 通过ECC操作。 冗余修复操作包括数据线修复和块修复。 ECC操作可以改变对应于包括“失败”单元的每单位存储器单元的数据的码字，并且还可以改变关于改变的码字的奇偶校验位的大小。

公开(公告)号：US20120117443A1

公开(公告)日：2012-05-10

申请号：US13239156

申请日：2011-09-21

申请人： Jin-il Lee ,  Dong-min Kim ,  Young-soo Sohn ,  Kwang-il Park

发明人： Jin-il Lee ,  Dong-min Kim ,  Young-soo Sohn ,  Kwang-il Park

IPC分类号： G06F11/08

CPC分类号： H03M13/09 ,  H04L1/0061

摘要： A data processing device for transmitting a first data includes a data generator configured to provide the first data, a cyclic redundancy check (CRC) generator configured to generate a CRC information having at least one bit whose binary value is modified in response to a toggle information, and a data transmitter configured to combine the CRC information and the first data as a combined data and output the combined data in serial.A data processing method for transmitting a first data includes a step of generating a first data, a step of generating cyclic redundancy check (CRC) information having at least one bit whose binary value is modified in response to a toggle information, and a step of generating a combined data by combining the generated CRC information and the first data as a combined data and outputting the combined data in serial.

摘要翻译： 一种用于发送第一数据的数据处理装置包括被配置为提供第一数据的数据生成器，循环冗余校验（CRC）发生器，被配置为生成具有响应于切换信息修改其二进制值的至少一个比特的至少一个比特的CRC信息 以及数据发送器，被配置为组合CRC信息和第一数据作为组合数据，并串行输出组合数据。 用于发送第一数据的数据处理方法包括产生第一数据的步骤，产生具有响应于切换信息修改其二进制值的至少一个比特的循环冗余校验（CRC）信息的步骤，以及步骤 通过组合生成的CRC信息和第一数据作为组合数据来生成组合数据，并串行输出组合数据。

公开(公告)号：US20110309468A1

公开(公告)日：2011-12-22

申请号：US13088442

申请日：2011-04-18

申请人： Tae-young Oh ,  Kwang-il Park ,  Seung-jun Bae ,  Yun-seok Yang ,  Young-soo Sohn ,  Si-hong Kim

发明人： Tae-young Oh ,  Kwang-il Park ,  Seung-jun Bae ,  Yun-seok Yang ,  Young-soo Sohn ,  Si-hong Kim

IPC分类号： H01L23/58 ,  H01L21/58

CPC分类号： H01L25/0657 ,  H01L24/16 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2224/05552

摘要： A semiconductor chip package includes a substrate, a first layer disposed on the substrate and a second layer substantially similar to and disposed on the first layer. The first layer has a first input/output (I/O) circuit, a first through-via connected to the first input/output (I/O) circuit and a second through-via that is not connected to the first I/O circuit. The second layer has a second I/O circuit, a third through-via connected to the second I/O circuit and a fourth through-via that is not connected to the second I/O circuit. The first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via. The package maybe fabricated by stacking the layers, and changing the orientation of the second layer relative to the first to ensure that the first through-via is connected to the fourth through-via, and the second through-via is connected to the third through-via.

摘要翻译： 半导体芯片封装包括衬底，设置在衬底上的第一层和与第一层基本相似并且布置在第一层上的第二层。 第一层具有第一输入/输出（I / O）电路，连接到第一输入/输出（I / O）电路的第一通孔和未连接到第一I / O的第二通孔 电路。 第二层具有第二I / O电路，连接到第二I / O电路的第三通孔和未连接到第二I / O电路的第四通孔。 第一通孔连接到第四通孔，第二通孔连接到第三通孔。 封装可以通过堆叠层制造，并且相对于第一层改变第二层的取向以确保第一通孔连接到第四通孔，而第二通孔连接到第三通孔 -通过。

公开(公告)号：US20110292742A1

公开(公告)日：2011-12-01

申请号：US13085776

申请日：2011-04-13

申请人： Tae-Young Oh ,  Kwang-il Park ,  Yun-Seok Yang ,  Young-Soo Sohn ,  Si-Hong Kim ,  Seung-Jun Bae

发明人： Tae-Young Oh ,  Kwang-il Park ,  Yun-Seok Yang ,  Young-Soo Sohn ,  Si-Hong Kim ,  Seung-Jun Bae

IPC分类号： G11C7/10 ,  H01L23/48

CPC分类号： G11C29/702 ,  G11C7/10 ,  H01L22/22 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/06541

摘要： A stacked semiconductor memory device according to the inventive concepts may include a plurality of memory chips stacked above a processor chip, a plurality of TSVs, and I/O buffers. The TSVs may pass through the memory chips and are connected to the processor chip. I/O buffers may be coupled between all or part of the memory chips and the TSVs and may be selectively activated on the basis of defective states of the TSVs.

摘要翻译： 根据本发明构思的叠层半导体存储器件可以包括堆叠在处理器芯片上方的多个存储器芯片，多个TSV和I / O缓冲器。 TSV可以通过存储器芯片并且连接到处理器芯片。 I / O缓冲器可以耦合在所有或部分存储器芯片和TSV之间，并且可以基于TSV的故障状态来选择性地激活。

公开(公告)号：US09059698B2

公开(公告)日：2015-06-16

申请号：US13240635

申请日：2011-09-22

申请人： Su-yeon Doo ,  Seung-jun Bae ,  Kwang-il Park ,  Young-soo Sohn

发明人： Su-yeon Doo ,  Seung-jun Bae ,  Kwang-il Park ,  Young-soo Sohn

IPC分类号： G05F1/00 ,  H03K19/003 ,  G05F1/575

CPC分类号： H03K19/00361 ,  G05F1/575

摘要： An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit.

摘要翻译： 集成电路装置包括被配置为耦合到外部电源的外部电源输入和在其电源输入处产生噪声的数字电路，例如时钟信号发生器电路。 该装置还包括复制负载电路和耦合到外部电源输入的电源电路，数字电路的电源输入和复制负载电路的电源输入。 电源电路被配置为响应于复制负载电路的电源输入处的电压来选择性地将外部电源节点耦合到数字电路的电源输入。 复制负载电路可以被配置为提供响应于数字电路的电源输入处的电压而变化的负载。

公开(公告)号：US08645790B2

公开(公告)日：2014-02-04

申请号：US13239156

申请日：2011-09-21

申请人： Jin-il Lee ,  Dong-min Kim ,  Young-soo Sohn ,  Kwang-il Park

发明人： Jin-il Lee ,  Dong-min Kim ,  Young-soo Sohn ,  Kwang-il Park

IPC分类号： H03M13/00

CPC分类号： H03M13/09 ,  H04L1/0061

摘要： A data processing device for transmitting a first data includes a data generator configured to provide the first data, a cyclic redundancy check (CRC) generator configured to generate a CRC information having at least one bit whose binary value is modified in response to a toggle information, and a data transmitter configured to combine the CRC information and the first data as a combined data and output the combined data in serial. A data processing method for transmitting a first data includes a step of generating a first data, a step of generating cyclic redundancy check (CRC) information having at least one bit whose binary value is modified in response to a toggle information, and a step of generating a combined data by combining the generated CRC information and the first data as a combined data and outputting the combined data in serial.

摘要翻译： 一种用于发送第一数据的数据处理装置包括被配置为提供第一数据的数据生成器，循环冗余校验（CRC）发生器，被配置为生成具有响应于切换信息修改其二进制值的至少一个比特的至少一个比特的CRC信息 以及数据发送器，被配置为组合CRC信息和第一数据作为组合数据，并串行输出组合数据。 用于发送第一数据的数据处理方法包括产生第一数据的步骤，产生具有响应于切换信息修改其二进制值的至少一个比特的循环冗余校验（CRC）信息的步骤，以及步骤 通过组合生成的CRC信息和第一数据作为组合数据来生成组合数据，并串行输出组合数据。

公开(公告)号：US20120086490A1

公开(公告)日：2012-04-12

申请号：US13240635

申请日：2011-09-22

申请人： Su-yeon Doo ,  Seung-jun Bae ,  Kwang-il Park ,  Young-soo Sohn

发明人： Su-yeon Doo ,  Seung-jun Bae ,  Kwang-il Park ,  Young-soo Sohn

IPC分类号： H03K3/023 ,  G05F1/10

CPC分类号： H03K19/00361 ,  G05F1/575

摘要： An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit.

摘要翻译： 集成电路装置包括被配置为耦合到外部电源的外部电源输入和在其电源输入处产生噪声的数字电路，例如时钟信号发生器电路。 该装置还包括复制负载电路和耦合到外部电源输入的电源电路，数字电路的电源输入和复制负载电路的电源输入。 电源电路被配置为响应于复制负载电路的电源输入处的电压来选择性地将外部电源节点耦合到数字电路的电源输入。 复制负载电路可以被配置为提供响应于数字电路的电源输入处的电压而变化的负载。

公开(公告)号：US07814239B2

公开(公告)日：2010-10-12

申请号：US12045289

申请日：2008-03-10

申请人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

发明人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

IPC分类号： G06F3/00

CPC分类号： G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

摘要翻译： 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。