公开(公告)号：US20050164445A1

公开(公告)日：2005-07-28

申请号：US10763643

申请日：2004-01-23

申请人： Yu Lin ,  Ming-Fang Wang ,  Kun-Chih Lee ,  Ming-Ho Yang ,  Liang-Gi Yo ,  Shih-Chang Chen ,  Karen Mai

发明人： Yu Lin ,  Ming-Fang Wang ,  Kun-Chih Lee ,  Ming-Ho Yang ,  Liang-Gi Yo ,  Shih-Chang Chen ,  Karen Mai

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/66833 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/10873 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for fabricating a portion of an integrated circuit on a semiconductor substrate. The method includes cleaning the surface of the substrate, and forming a thin insulate over the substrate. The method also includes depositing a high dielectric constant (high-k) material over the thin insulate, and then performing a hydrogen-based anneal on the high-k material. The method further includes performing an oxygen-based anneal on the high-k material, wherein the hydrogen-based and oxygen-based anneals occur sequentially.

摘要翻译： 一种在半导体衬底上制造集成电路的一部分的方法。 该方法包括清洗基底的表面，并在基底上形成薄的绝缘体。 该方法还包括在薄绝缘体上沉积高介电常数（高k）材料，然后在高k材料上进行氢基退火。 所述方法还包括对所述高k材料进行氧基退火，其中所述氢基和氧基退火依次发生。

公开(公告)号：US07037816B2

公开(公告)日：2006-05-02

申请号：US10763643

申请日：2004-01-23

申请人： Yu Min Lin ,  Ming-Fang Wang ,  Kun-Chih Lee ,  Ming-Ho Yang ,  Liang-Gi Yo ,  Shih-Chang Chen ,  Karen L. Mai

发明人： Yu Min Lin ,  Ming-Fang Wang ,  Kun-Chih Lee ,  Ming-Ho Yang ,  Liang-Gi Yo ,  Shih-Chang Chen ,  Karen L. Mai

IPC分类号： H01L21/4763

CPC分类号： H01L29/66833 ,  H01L21/28194 ,  H01L21/28202 ,  H01L27/10873 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for fabricating a portion of an integrated circuit on a semiconductor substrate. The method includes cleaning the surface of the substrate, and forming a thin insulate over the substrate. The method also includes depositing a high dielectric constant (high-k) material over the thin insulate, and then performing a hydrogen-based anneal on the high-k material. The method further includes performing an oxygen-based anneal on the high-k material, wherein the hydrogen-based and oxygen-based anneals occur sequentially.

摘要翻译： 一种在半导体衬底上制造集成电路的一部分的方法。 该方法包括清洗基底的表面，并在基底上形成薄的绝缘体。 该方法还包括在薄绝缘体上沉积高介电常数（高k）材料，然后在高k材料上进行氢基退火。 所述方法还包括对所述高k材料进行氧基退火，其中所述氢基和氧基退火依次发生。

公开(公告)号：US20060154425A1

公开(公告)日：2006-07-13

申请号：US11032439

申请日：2005-01-10

申请人： Ming-Ho Yang ,  Karen Mai ,  Liang-Gi Yao ,  Shih-Chang Chen

发明人： Ming-Ho Yang ,  Karen Mai ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28061 ,  H01L21/28194 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device and method for fabricating the same. The semiconductor device comprises a substrate with a gate stack thereon, wherein the gate stack comprises a high-k dielectric layer and a conductive layer sequentially overlying a portion of the substrate. An oxidation-proof layer overlies sidewalls of the gate stack. A pair of insulating spacers oppositely overlies sidewalls of the gate stack and the oxidation-proof layers thereon and a pair of source/drain regions is oppositely formed in the substrate adjacent to the gate stack, wherein the oxidation-proof layer suppresses oxidation encroachment between the gate stack and the substrate.

摘要翻译： 一种半导体器件及其制造方法。 半导体器件包括其上具有栅极堆叠的衬底，其中栅极堆叠包括高k电介质层和顺序地覆盖衬底的一部分的导电层。 防氧化层覆盖在栅叠层的侧壁上。 一对绝缘隔片相对地覆盖在栅堆叠的侧壁和其上的防氧化层上，并且一对源极/漏极区域相邻地形成在与栅极叠层相邻的衬底中，其中防氧化层抑制了栅极叠层之间的氧化侵蚀 栅极堆叠和衬底。

公开(公告)号：US20060035477A1

公开(公告)日：2006-02-16

申请号：US10916495

申请日：2004-08-12

申请人： Karen Mai ,  Ming-Ho Yang ,  Tze Lee ,  Shih-Chang Chen ,  Chun-Feng Nieh

发明人： Karen Mai ,  Ming-Ho Yang ,  Tze Lee ,  Shih-Chang Chen ,  Chun-Feng Nieh

IPC分类号： H01L21/477 ,  F27D11/00

CPC分类号： F27D99/0006 ,  F27B17/0025 ,  F27D5/0037 ,  F27D2099/0026 ,  H01L21/67115 ,  H01L21/67248

摘要： Methods for rapid thermal processing of semiconductor substrates are provided. An exemplary method comprises directing radiant heat energy emitted from a heat source toward a backside surface of the semiconductor substrate. Systems for rapid thermal processing also are provided.

摘要翻译： 提供了半导体衬底的快速热处理方法。 一种示例性的方法包括将从热源发射的辐射热能引导到半导体衬底的背面。 还提供用于快速热处理的系统。

公开(公告)号：US20110318915A1

公开(公告)日：2011-12-29

申请号：US13224059

申请日：2011-09-01

申请人： Liang-Gi Yao ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

发明人： Liang-Gi Yao ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

IPC分类号： H01L21/28 ,  B82Y40/00

CPC分类号： H01L21/0228 ,  C23C16/56 ,  H01L21/02145 ,  H01L21/02153 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L29/4966 ,  H01L29/517

摘要： A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.

摘要翻译： 一种减少高k电介质层中的杂质的方法，包括以下步骤。 提供基板。 在衬底上形成具有杂质的高k电介质层。 高k电介质层由MOCVD或ALCVD工艺形成。 退火高k电介质层以减少高k电介质层内的杂质。

公开(公告)号：US07351994B2

公开(公告)日：2008-04-01

申请号：US10762164

申请日：2004-01-21

申请人： Liang-Gi Yao ,  Tien-Chih Chang ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

发明人： Liang-Gi Yao ,  Tien-Chih Chang ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

IPC分类号： H01L29/06 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054

摘要： At least one high-k device, and a method for forming the at least one high-k device, comprising the following. A structure having a strained substrate formed thereover. The strained substrate comprising at least an uppermost strained-Si epi layer. At least one dielectric gate oxide portion over the strained substrate. The at least one dielectric gate oxide portion having a dielectric constant of greater than about 4.0. A device over each of the at least one dielectric gate oxide portion to complete the least one high-k device. A method of forming the at least one high-k device.

摘要翻译： 至少一个高k装置和用于形成至少一个高k装置的方法包括以下。 具有在其上形成的应变衬底的结构。 应变衬底包括至少最上层的应变Si外延层。 在应变衬底上的至少一个电介质栅极氧化物部分。 所述至少一个电介质栅极氧化物部分具有大于约4.0的介电常数。 在所述至少一个电介质栅极氧化物部分中的每一个上方的器件，以完成所述至少一个高k器件。 一种形成所述至少一个高k装置的方法。

公开(公告)号：US06914313B2

公开(公告)日：2005-07-05

申请号：US10696007

申请日：2003-10-29

申请人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

发明人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC分类号： H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  Y10S257/90

摘要： A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

摘要翻译： 已经开发了CMOS器件结构，以及制造具有由高k金属氧化物层构成的栅极绝缘体层的CMOS器件的方法。 在沉积高k金属氧化物层之前，该工艺特征是形成凹陷的，重掺杂的源极/漏极区域以及垂直的多晶硅LDD间隔物。 先前用作凹陷区域的掩模的氮化硅形状的去除，其又用于重掺杂源极/漏极区域的适应，提供了由高k金属氧化物层占据的空间。 通过延迟沉积金属氧化物层，在高温下进行保存，通过垂直多晶硅间隔物对接的高k栅极绝缘体层的完整性，并覆盖由半导体衬底的非凹陷部分提供的沟道区域 退火如重掺杂源极/漏极区的激活退火，以及用于金属硅化物形成的退火。

公开(公告)号：US08785272B2

公开(公告)日：2014-07-22

申请号：US13224059

申请日：2011-09-01

申请人： Liang-Gi Yao ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

发明人： Liang-Gi Yao ,  Ming-Fang Wang ,  Shih-Chang Chen ,  Mong-Song Liang

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L21/314

CPC分类号： H01L21/0228 ,  C23C16/56 ,  H01L21/02145 ,  H01L21/02153 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L29/4966 ,  H01L29/517

摘要： A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.

摘要翻译： 一种减少高k电介质层中的杂质的方法，包括以下步骤。 提供基板。 在衬底上形成具有杂质的高k电介质层。 高k电介质层由MOCVD或ALCVD工艺形成。 退火高k电介质层以减少高k电介质层内的杂质。

公开(公告)号：US07303996B2

公开(公告)日：2007-12-04

申请号：US10677158

申请日：2003-10-01

申请人： Ming-Fang Wang ,  Tuo-Hung Hou ,  Kai-Lin Mai ,  Liang-Gi Yao ,  Shih-Chang Chen

发明人： Ming-Fang Wang ,  Tuo-Hung Hou ,  Kai-Lin Mai ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC分类号： H01L21/302

CPC分类号： H01L21/28185 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for treating a gate structure comprising a high-K gate dielectric stack to improve electric performance characteristics including providing a gate dielectric layer stack including a binary oxide over a silicon substrate; forming a polysilicon layer over the gate dielectric layer stack; lithographically patterning and etching to form a gate structure; and, carrying out at least one plasma treatment of the gate structure comprising a plasma source gas selected from the group consisting of H2, N2, O2, and NH3.

摘要翻译： 一种用于处理包括高K栅极电介质堆叠的栅极结构以改善电性能特性的方法，包括在硅衬底上提供包括二元氧化物的栅极介电层堆叠; 在所述栅极介电层堆叠上形成多晶硅层; 光刻图案化和蚀刻以形成栅极结构; 以及进行至少一种栅极结构的等离子体处理，所述栅极结构包括选自H 2，N 2，O 2， / SUB>和NH 3。

公开(公告)号：US20050196927A1

公开(公告)日：2005-09-08

申请号：US11119951

申请日：2005-05-02

申请人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

发明人： Ming-Fang Wang ,  Chien-Hao Chen ,  Liang-Gi Yao ,  Shih-Chang Chen

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  Y10S257/90

摘要： A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.