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    3D TRANSMISSION LINES FOR SEMICONDUCTORS
    1.
    发明申请
    3D TRANSMISSION LINES FOR SEMICONDUCTORS 有权
    用于半导体的3D传输线

    公开(公告)号：US20130234305A1

    公开(公告)日：2013-09-12

    申请号：US13415906

    申请日：2012-03-09

    申请人： Yu-Ling LIN ,  Hsiao-Tsung YEN ,  Feng Wei KUO ,  Ho-Hsiang CHEN ,  Chin-Wei KUO

    发明人： Yu-Ling LIN ,  Hsiao-Tsung YEN ,  Feng Wei KUO ,  Ho-Hsiang CHEN ,  Chin-Wei KUO

    IPC分类号： H01L23/58 ,  H01L21/28

    CPC分类号： H01L23/60 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/66 ,  H01L25/0657 ,  H01L2223/6627 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A transmission line structure for semiconductor RF and wireless circuits, and method for forming the same. The transmission line structure includes embodiments having a first die including a first substrate, a first insulating layer, and a ground plane, and a second die including a second substrate, a second insulating layer, and a signal transmission line. The second die may be positioned above and spaced apart from the first die. An underfill is disposed between the ground plane of the first die and the signal transmission line of the second die. Collectively, the ground plane and transmission line of the first and second die and underfill forms a compact transmission line structure. In some embodiments, the transmission line structure may be used for microwave applications.

    摘要翻译： 用于半导体RF和无线电路的传输线结构及其形成方法。 传输线结构包括具有包括第一衬底，第一绝缘层和接地平面的第一裸片的实施例，以及包括第二衬底，第二绝缘层和信号传输线的第二裸片。 第二管芯可以位于第一管芯的上方并与之隔开。 在第一管芯的接地面和第二管芯的信号传输线之间设置底部填充物。 总的来说，第一和第二模具和底部填充物的接地平面和传输线形成紧凑的传输线结构。 在一些实施例中，传输线结构可用于微波应用。

    TRANSFORMER WITH BYPASS CAPACITOR
    2.
    发明申请
    TRANSFORMER WITH BYPASS CAPACITOR 有权
    带旁路电容器的变压器

    公开(公告)号：US20120146741A1

    公开(公告)日：2012-06-14

    申请号：US12963701

    申请日：2010-12-09

    申请人： Hsiao-Tsung YEN ,  Yu-Ling Lin ,  Ying-Ta Lu ,  Chin-Wei Kuo ,  Ho-Hsiang Chen

    发明人： Hsiao-Tsung YEN ,  Yu-Ling Lin ,  Ying-Ta Lu ,  Chin-Wei Kuo ,  Ho-Hsiang Chen

    IPC分类号： H03H7/42 ,  H01L21/00

    CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F2017/0086 ,  H01L23/5223 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

    摘要： An electronic device comprises first, second and third inductors connected in series and formed in a metal layer over a semiconductor substrate. The first and second inductors have a mutual inductance with each other. The second and third inductors having a mutual inductance with each other. A first capacitor has a first electrode connected to a first node. The first node is conductively coupled between the first and second inductors. A second capacitor has a second electrode connected to a second node. The second node is conductively coupled between the second and third inductors.

    摘要翻译： 电子器件包括串联连接并形成在半导体衬底上的金属层中的第一，第二和第三电感器。 第一和第二电感器具有彼此的互感。 第二和第三电感器具有彼此的互感。 第一电容器具有连接到第一节点的第一电极。 第一节点电导耦合在第一和第二电感器之间。 第二电容器具有连接到第二节点的第二电极。 第二节点电导耦合在第二和第三电感器之间。

    SYSTEM AND METHOD FOR MODELING THROUGH SILICON VIA
    4.
    发明申请
    SYSTEM AND METHOD FOR MODELING THROUGH SILICON VIA 有权
    通过硅建模的系统和方法

    公开(公告)号：US20130246990A1

    公开(公告)日：2013-09-19

    申请号：US13419959

    申请日：2012-03-14

    申请人： Hsiao-Tsung YEN ,  Yu-Ling Lin ,  Chin-Wei Kuo

    发明人： Hsiao-Tsung YEN ,  Yu-Ling Lin ,  Chin-Wei Kuo

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/16225 ,  H01L2924/15311

    摘要： A computer implemented system comprises a processor programmed to analyze a circuit to determine a response of the circuit to an input radio frequency (RF) signal, for at least one of designing, manufacturing, and testing the circuit. An interposer model is tangibly embodied in a non-transitory machine readable storage medium to be accessed by the processor. The interposer model is processed by the computer to output data representing a response of a though substrate via (TSV) to the radio frequency (RF) signal. The interposer model comprises a plurality of TSV models. Each TSV model has a respective three-port network. One of the ports of each three-port network is a floating node. The floating nodes of each of the three-port networks are connected to each other.

    摘要翻译： 计算机实现的系统包括被编程为分析电路以确定电路对输入射频（RF）信号的响应的处理器，用于设计，制造和测试电路中的至少一个。 中介层模型有形地体现在待处理器访问的非暂时机器可读存储介质中。 内插器模型由计算机处理以将表示通过（TSV）的基板的响应的数据输出到射频（RF）信号。 内插器模型包括多个TSV模型。 每个TSV模型都有相应的三端口网络。 每个三端口网络的一个端口是浮动节点。 每个三端口网络的浮动节点彼此连接。

    INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME
    5.
    发明申请
    INTEGRATED CIRCUITS AND METHODS OF FORMING THE SAME 有权
    集成电路及其形成方法

    公开(公告)号：US20110298551A1

    公开(公告)日：2011-12-08

    申请号：US12795734

    申请日：2010-06-08

    申请人： Hsiao-Tsung YEN ,  Hsien-Pin HU ,  Jhe-Ching LU ,  Chin-Wei KUO ,  Ming-Fa CHEN ,  Sally LIU

    发明人： Hsiao-Tsung YEN ,  Hsien-Pin HU ,  Jhe-Ching LU ,  Chin-Wei KUO ,  Ming-Fa CHEN ,  Sally LIU

    IPC分类号： H03B5/12 ,  H01L21/329 ,  H01L29/93

    CPC分类号： H01L27/016 ,  H01L29/93

    摘要： A three-dimensional integrated circuit includes a semiconductor substrate where the substrate has an opening extending through a first surface and a second surface of the substrate and where the first surface and the second surface are opposite surfaces of the substrate. A conductive material substantially fills the opening of the substrate to form a conductive through-substrate-via (TSV). An active circuit is disposed on the first surface of the substrate, an inductor is disposed on the second surface of the substrate and the TSV is electrically coupled to the active circuit and the inductor. The three-dimensional integrated circuit may include a varactor formed from a dielectric layer formed in the opening of the substrate such that the conductive material is disposed adjacent the dielectric layer and an impurity implanted region disposed surrounding the TSV such that the dielectric layer is formed between the impurity implanted region and the TSV.

    摘要翻译： 三维集成电路包括半导体衬底，其中衬底具有延伸穿过衬底的第一表面和第二表面的开口，并且第一表面和第二表面与衬底相对的表面。 导电材料基本上填充衬底的开口以形成导电的通过衬底通孔（TSV）。 有源电路设置在衬底的第一表面上，电感器设置在衬底的第二表面上，并且TSV电耦合到有源电路和电感器。 三维集成电路可以包括由形成在基板的开口中的电介质层形成的变容二极管，使得导电材料邻近介电层设置，以及设置在TSV周围的杂质注入区域，使得介电层形成在 杂质注入区和TSV。

    VOLTAGE-CONTROLLED OSCILLATOR
    6.
    发明申请
    VOLTAGE-CONTROLLED OSCILLATOR 有权
    电压控制振荡器

    公开(公告)号：US20130154752A1

    公开(公告)日：2013-06-20

    申请号：US13325442

    申请日：2011-12-14

    申请人： Ying-Ta LU ,  Hsien-Yuan LIAO ,  Hsiao-Tsung YEN ,  Ho-Hsiang CHEN ,  Chewn-Pu JOU

    发明人： Ying-Ta LU ,  Hsien-Yuan LIAO ,  Hsiao-Tsung YEN ,  Ho-Hsiang CHEN ,  Chewn-Pu JOU

    IPC分类号： H03B5/12

    CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/124 ,  H03B5/1852

    摘要： A voltage-controlled oscillator circuit includes a first transistor, a second transistor, a first resonator circuit, a second resonator circuit, a first current path and a second current path. A drain of the first transistor is coupled to a gate of the second transistor and to a first end of the first resonator circuit. A source of the first transistor is coupled to the first current path and to a first end of the second resonator circuit. A drain of the second transistor is coupled to a gate of the first transistor and to a second end of the first resonator circuit. A source of the second transistor is coupled to the second current path and a second end of the second resonator circuit.

    摘要翻译： 压控振荡器电路包括第一晶体管，第二晶体管，第一谐振器电路，第二谐振器电路，第一电流路径和第二电流路径。 第一晶体管的漏极耦合到第二晶体管的栅极和第一谐振器电路的第一端。 第一晶体管的源极耦合到第一电流路径和第二谐振器电路的第一端。 第二晶体管的漏极耦合到第一晶体管的栅极和第一谐振器电路的第二端。 第二晶体管的源极耦合到第二电流路径和第二谐振器电路的第二端。