公开(公告)号：US08643149B2

公开(公告)日：2014-02-04

申请号：US12683604

申请日：2010-01-07

申请人： Ming-Fa Chen

发明人： Ming-Fa Chen

IPC分类号： H01L23/48 ,  H01L23/498

CPC分类号： H01L24/10 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/522 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

摘要： Stress barrier structures for semiconductor chips, and methods of fabrication thereof are described. In one embodiment, the semiconductor device includes a semiconductor substrate that includes active circuitry and an interconnect metallization structure over the active circuitry, wherein the interconnect metallization structure includes a layer of low-k insulating layer. A first metal bump is disposed over the semiconductor substrate and coupled to the active circuitry of the semiconductor substrate. A first stress barrier structure is disposed under the metal bump, and disposed over the low-k insulating layer, and a second substrate is disposed over the first metal bump.

摘要翻译： 描述了用于半导体芯片的应力阻挡结构及其制造方法。 在一个实施例中，半导体器件包括半导体衬底，其包括有源电路和在有源电路上的互连金属化结构，其中互连金属化结构包括低k绝缘层的层。 第一金属凸块设置在半导体衬底上并耦合到半导体衬底的有源电路。 第一应力阻挡结构设置在金属凸块下方，并且设置在低k绝缘层上，并且第二基板设置在第一金属凸块的上方。

公开(公告)号：US08624324B1

公开(公告)日：2014-01-07

申请号：US13572337

申请日：2012-08-10

申请人： Ming-Fa Chen ,  Yu-Young Wang ,  Sen-Bor Jan

发明人： Ming-Fa Chen ,  Yu-Young Wang ,  Sen-Bor Jan

IPC分类号： H01L29/423 ,  H01L21/28

CPC分类号： H01L23/481 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/76829 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41758 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and devices for connecting a through via and a terminal of a transistor formed of a strained silicon material are provided. The terminal, which can be a source or a drain of a NMOS or a PMOS transistor, is formed within a substrate. A first contact within a first inter-layer dielectric (ILD) layer over the substrate is formed over and connected to the terminal. A through via extends through the first ILD layer into the substrate. A second contact is formed over and connected to the first contact and the through via within a second ILD layer and a contact etch stop layer (CESL). The second ILD layer is over the CESL, and the CESL is over the first ILD layer, which are all below a first inter-metal dielectric (IMD) layer and the first metal layer of the transistor.

摘要翻译： 提供了用于连接由应变硅材料形成的晶体管的通孔和端子的方法和装置。 作为NMOS或PMOS晶体管的源极或漏极的端子形成在衬底内。 在衬底上的第一层间电介质（ILD）层内的第一接触形成在端子上并连接到端子。 通孔延伸穿过第一ILD层进入衬底。 在第二ILD层和接触蚀刻停止层（CESL）内形成第二触点并连接到第一触点和穿通通孔。 第二ILD层在CESL之上，并且CESL在第一ILD层之上，它们都在第一金属间电介质（IMD）层和晶体管的第一金属层的下面。

公开(公告)号：US08399354B2

公开(公告)日：2013-03-19

申请号：US12617259

申请日：2009-11-12

申请人： Ming-Fa Chen

发明人： Ming-Fa Chen

IPC分类号： H01L21/44

CPC分类号： H01L23/481 ,  H01L21/3065 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/6836 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13009 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/059 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

摘要： A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.

公开(公告)号：US08378480B2

公开(公告)日：2013-02-19

申请号：US12717779

申请日：2010-03-04

申请人： Ming-Fa Chen ,  Chia-Yen Lee

发明人： Ming-Fa Chen ,  Chia-Yen Lee

IPC分类号： H01L23/12 ,  H01L21/00

CPC分类号： H01L23/52 ,  H01L24/97 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00

摘要： A package structure includes a first die, and a second die over and bonded to the first die. The second die has a size smaller than a size of the first die. A dummy chip is over and bonded onto the first die. The dummy chip includes a portion encircling the second die. The dummy chip includes a material selected from the group consisting essentially of silicon and a metal.

摘要翻译： 包装结构包括第一模具和第二模具，并且结合到第一模具。 第二模具的尺寸小于第一模具的尺寸。 虚拟芯片结束并结合到第一裸片上。 虚设芯片包括环绕第二模具的部分。 虚设芯片包括选自基本上由硅和金属组成的组的材料。

公开(公告)号：US08310328B2

公开(公告)日：2012-11-13

申请号：US12899836

申请日：2010-10-07

申请人： Hung Yi Lin ,  Ming Fa Chen

发明人： Hung Yi Lin ,  Ming Fa Chen

IPC分类号： H01F5/00 ,  H01F27/28 ,  H01L27/08

CPC分类号： H01F41/042 ,  H01F5/003 ,  H01L21/76 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49146

摘要： A method of making a planar coil is disclosed in the present invention. First, a substrate having a trench is provided. Then, a barrier and a seed layer are formed on the substrate in sequence. An isolative layer is used for guiding a conductive material to flow into a lower portion of the trench such that accumulation of the conductive material at opening of the trench is prevented before the lower portion of the trench is completely filled up, thereby avoiding gap formation in the trench.

摘要翻译： 在本发明中公开了制造平面线圈的方法。 首先，提供具有沟槽的衬底。 然后，依次在基板上形成阻挡层和种子层。 隔离层用于引导导电材料流入沟槽的下部，使得沟槽开口处的导电材料的积聚在沟槽的下部被完全填充之前被阻止，从而避免了在沟槽中的间隙形成 沟渠。

公开(公告)号：US08288872B2

公开(公告)日：2012-10-16

申请号：US12186105

申请日：2008-08-05

申请人： Ming-Fa Chen ,  Chen-Shien Chen

发明人： Ming-Fa Chen ,  Chen-Shien Chen

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2224/05552

摘要： A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die.

摘要翻译： 公开了一种用于形成凹凸金属化层的系统和方法，其通过硅通孔和迹线减少了UBM的总体占地面积。 优选实施例包括在多个通孔上形成凸起下金属化层，而UBM仅连接到其所位于的硅通孔总数的一部分。 连接到贯通硅通孔的迹线可另外形成在UBM之下，以在模具表面上节省更多的空间。

公开(公告)号：US20120012997A1

公开(公告)日：2012-01-19

申请号：US12835189

申请日：2010-07-13

申请人： Wen-Wei Shen ,  Yao-Chun Chuang ,  Chen-Shien Chen ,  Ming-Fa Chen

发明人： Wen-Wei Shen ,  Yao-Chun Chuang ,  Chen-Shien Chen ,  Ming-Fa Chen

IPC分类号： H01L23/50 ,  H01L21/60 ,  H01L21/98

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/023 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/10126 ,  H01L2224/10156 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13564 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13669 ,  H01L2224/13684 ,  H01L2224/16148 ,  H01L2224/81193 ,  H01L2224/81898 ,  H01L2225/06513 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/01007 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00

摘要： A bump structure that may be used to interconnect one substrate to another substrate is provided. A recessed conductive pillar is formed on a first substrate such that the recessed conductive pillar has a recess formed therein. The recess may be filled with a solder material. A conductive pillar on a second substrate may be formed having a contact surface with a width less than or equal to a width of the recess. The first substrate may be attached to the second substrate such that the conductive pillar on the second substrate is positioned over or in the recess of the first substrate. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.

摘要翻译： 提供了可用于将一个衬底互连到另一衬底的凸块结构。 凹陷的导电柱形成在第一基板上，使得凹入的导电柱具有形成在其中的凹部。 凹部可以填充有焊料材料。 第二基板上的导电柱可以形成为具有宽度小于或等于凹部宽度的接触表面。 第一衬底可以附接到第二衬底，使得第二衬底上的导电柱位于第一衬底的凹部中或其中。 基板可以各自为集成电路管芯，插入件，印刷电路板，高密度互连等。

公开(公告)号：US20110285023A1

公开(公告)日：2011-11-24

申请号：US12784266

申请日：2010-05-20

申请人： Wen-Wei Shen ,  Ying-Ching Shih ,  Chen-Shien Chen ,  Ming-Fa Chen

发明人： Wen-Wei Shen ,  Ying-Ching Shih ,  Chen-Shien Chen ,  Ming-Fa Chen

IPC分类号： H01L23/528 ,  H01L21/50

CPC分类号： H01L25/0657 ,  H01L21/486 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0381 ,  H01L2224/03831 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/1162 ,  H01L2224/11622 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1354 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2224/05552 ,  H01L2924/00

摘要： A bump structure that may be used to interconnect one substrate to another substrate is provided. A conductive pillar is formed on a first substrate such that the conductive pillar has a width different than a contact surface on a second substrate. In an embodiment the conductive pillar of the first substrate has a trapezoidal shape or a shape having tapered sidewalls, thereby providing a conductive pillar having base portion wider than a tip portion. The substrates may each be an integrated circuit die, an interposer, a printed circuit board, a high-density interconnect, or the like.

摘要翻译： 提供了可用于将一个衬底互连到另一衬底的凸块结构。 导电柱形成在第一基板上，使得导电柱的宽度不同于第二基板上的接触表面。 在一个实施例中，第一基板的导电柱具有梯形形状或具有锥形侧壁的形状，从而提供具有比尖端部宽的基部的导电柱。 基板可以各自为集成电路管芯，插入件，印刷电路板，高密度互连等。

公开(公告)号：US07910473B2

公开(公告)日：2011-03-22

申请号：US12347745

申请日：2008-12-31

申请人： Ming-Fa Chen

发明人： Ming-Fa Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L21/7682 ,  H01L23/481 ,  H01L23/5222 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the liner, which is subsequently removed to form an air gap around the conductive material of the through-silicon via. A dielectric layer is formed of the backside of the semiconductor substrate to seal the air gap.

摘要翻译： 提供一种半导体衬底，其具有穿过硅通孔和半导体衬底之间的气隙的通硅通孔。 部分地通过半导体衬底形成开口。 开口首先用衬里衬里，然后开口填充有导电材料。 半导体衬底的背面被薄化以暴露衬里，衬垫随后被去除以在通过硅通孔的导电材料周围形成气隙。 电介质层由半导体衬底的背面形成以密封气隙。

公开(公告)号：US06340547B1

公开(公告)日：2002-01-22

申请号：US09481032

申请日：2000-01-11

申请人： Ming-Fa Chen ,  Chih-Chien Hung ,  Chia-Hsiang Chen ,  Fu-Tien Wong

发明人： Ming-Fa Chen ,  Chih-Chien Hung ,  Chia-Hsiang Chen ,  Fu-Tien Wong

IPC分类号： G03F900

CPC分类号： G03F9/7003 ,  G03F7/70458 ,  G03F9/7046

摘要： A method of forming circuit patterns on a semiconductor wafer using two different image steppers having nonaligned optical image systems achieves optical alignment of multiple overlays with high accuracy. A first alignment mark is imaged by the first stepper onto a material layer deposited on the wafer, and a second alignment mark is imaged onto a subsequently deposited material layer using the second stepper. Alignment of the two marks, and thus of successively imaged, overlying circuit patterns, is achieved by translating the optical coordinates of the second alignment system into the those of the first alignment system, and then making corresponding two dimensional adjustment of the wafer position relative to the second stepper.

摘要翻译： 使用具有非对准光学图像系统的两个不同的图像步进器在半导体晶片上形成电路图案的方法实现了高精度的多个覆盖层的光学对准。 将第一对准标记由第一步进器成像到沉积在晶片上的材料层上，并且使用第二步进器将第二对准标记成像到随后沉积的材料层上。 通过将第二对准系统的光学坐标转换为第一对准系统的光学坐标，然后相对于第二对准系统的晶片位置进行相应的二维调整来实现两个标记的对准，并且因此连续成像的上覆电路图案的对准 第二步。