公开(公告)号：US20080102207A1

公开(公告)日：2008-05-01

申请号：US11715619

申请日：2007-03-08

申请人： Yu-Min Tsai ,  Hsiao-Che Wu ,  Wen-Li Tsai

发明人： Yu-Min Tsai ,  Hsiao-Che Wu ,  Wen-Li Tsai

IPC分类号： C23C16/00 ,  F16K21/00

CPC分类号： C23C16/45565 ,  C23C16/45572 ,  C23C16/481 ,  H01L21/67109 ,  H01L21/67115 ,  Y10T137/9464

摘要： A gas delivering system for an in situ thermal treatment, a thin film deposition and a use of the same are provided. The gas delivering system integrates a thermal treatment system therein so that a thin film deposition and a by rapid thermal annealing can be performed alternatively on a wafer in a reaction chamber. Accordingly, the density of the thin film can be improved and the thermal budget of the process can be reduced.

摘要翻译： 提供了一种用于原位热处理，薄膜沉积及其使用的气体输送系统。 气体输送系统将其中的热处理系统集成在一起，可以在反应室中的晶片上交替地进行薄膜沉积和快速热退火。 因此，可以提高薄膜的密度，并且可以降低该方法的热预算。

公开(公告)号：US07436526B2

公开(公告)日：2008-10-14

申请号：US11669165

申请日：2007-01-31

申请人： Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

发明人： Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

IPC分类号： B29C65/00 ,  B29C65/02 ,  B32B37/00 ,  B32B38/00 ,  C23C16/52 ,  C23C14/54 ,  G01B11/14 ,  G01B11/28

CPC分类号： C23C14/544 ,  G01B11/0625 ,  G01B11/0675 ,  G01B11/0683 ,  H01L22/12 ,  H01L22/20

摘要： A real-time system adapted to a PVD apparatus for monitoring and controlling film uniformity is described. The system includes a shielding plate, a monitoring device, and a data processing program. The shielding plate is disposed on an inner wall of a reaction chamber above a wafer stage. An opening in the center of the shielding plate exposes the wafer. The monitoring device including a scanner and a sensor respectively disposed on opposite sidewalls of the reaction chamber between the shielding plate and the wafer stage is used for measuring the flux of the particles on every portion of the wafer to acquire real-time uniformity data including a function of the wafer position and the flux. The data processing program compares the real-time uniformity data and reference uniformity data, and a feedback signal is outputted to the PVD apparatus to adjust the process parameter thereof for controlling film uniformity.

摘要翻译： 描述了适用于监测和控制膜均匀性的PVD设备的实时系统。 该系统包括屏蔽板，监视装置和数据处理程序。 屏蔽板设置在晶片台上方的反应室的内壁上。 屏蔽板中心的开口露出晶片。 包括扫描仪和分别设置在屏蔽板和晶片台之间的反应室的相对侧壁上的传感器的监视装置用于测量晶片每一部分上的颗粒的通量，以获得实时均匀性数据，包括 晶圆位置和通量的功能。 数据处理程序比较实时均匀性数据和参考均匀性数据，并且将反馈信号输出到PVD装置以调整其处理参数以控制膜均匀性。

公开(公告)号：US20080118631A1

公开(公告)日：2008-05-22

申请号：US11669165

申请日：2007-01-31

申请人： Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

发明人： Wen-Li Tsai ,  Yu-Min Tsai ,  Hsiao-Che Wu

IPC分类号： B05C11/00 ,  C23C14/54

CPC分类号： C23C14/544 ,  G01B11/0625 ,  G01B11/0675 ,  G01B11/0683 ,  H01L22/12 ,  H01L22/20

摘要： A real-time system adapted to a PVD apparatus for monitoring and controlling film uniformity is described. The system includes a shielding plate, a monitoring device, and a data processing program. The shielding plate is disposed on an inner wall of a reaction chamber above a wafer stage. An opening in the center of the shielding plate exposes the wafer. The monitoring device including a scanner and a sensor respectively disposed on opposite sidewalls of the reaction chamber between the shielding plate and the wafer stage is used for measuring the flux of the particles on every portion of the wafer to acquire real-time uniformity data including a function of the wafer position and the flux. The data processing program compares the real-time uniformity data and reference uniformity data, and a feedback signal is outputted to the PVD apparatus to adjust the process parameter thereof for controlling film uniformity.

摘要翻译： 描述了适用于监测和控制膜均匀性的PVD设备的实时系统。 该系统包括屏蔽板，监视装置和数据处理程序。 屏蔽板设置在晶片台上方的反应室的内壁上。 屏蔽板中心的开口露出晶片。 包括扫描仪和分别设置在屏蔽板和晶片台之间的反应室的相对侧壁上的传感器的监视装置用于测量晶片每一部分上的颗粒的通量，以获得实时均匀性数据，包括 晶圆位置和通量的功能。 数据处理程序比较实时均匀性数据和参考均匀性数据，并且将反馈信号输出到PVD装置以调整其处理参数以控制膜均匀性。

公开(公告)号：US07919384B2

公开(公告)日：2011-04-05

申请号：US12050649

申请日：2008-03-18

申请人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

发明人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC分类号： H01L21/20

CPC分类号： H01L28/91

摘要： A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

摘要翻译： 公开了制造半导体器件的平面型底电极的方法。 在基板上形成牺牲层结构。 在牺牲层结构中限定多个第一沟槽，其中这些第一沟槽被布置在第一方向上。 第一沟槽用绝缘材料填充，以在每个第一沟槽中形成绝缘层。 多个第二沟槽被限定在绝缘层之间的牺牲层结构中，并且被布置在第二方向上，使得第二沟槽与第一沟槽相交。 第二沟槽填充有底部电极材料，以在每个第二沟槽中形成底部电极层。 绝缘层分别分开彼此分离的底部电极层。 最后，去除牺牲层结构通过两个相邻的绝缘层和两个相邻的底部电极层限定了接收空间。

公开(公告)号：US20090023264A1

公开(公告)日：2009-01-22

申请号：US12050649

申请日：2008-03-18

申请人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

发明人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC分类号： H01L21/02

CPC分类号： H01L28/91

摘要： A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

摘要翻译： 公开了制造半导体器件的平面型底电极的方法。 在基板上形成牺牲层结构。 在牺牲层结构中限定多个第一沟槽，其中这些第一沟槽被布置在第一方向上。 第一沟槽用绝缘材料填充，以在每个第一沟槽中形成绝缘层。 多个第二沟槽被限定在绝缘层之间的牺牲层结构中，并且被布置在第二方向上，使得第二沟槽与第一沟槽相交。 第二沟槽填充有底部电极材料，以在每个第二沟槽中形成底部电极层。 绝缘层分别分开彼此分离的底部电极层。 最后，去除牺牲层结构通过两个相邻的绝缘层和两个相邻的底部电极层限定了接收空间。

公开(公告)号：US20090039428A1

公开(公告)日：2009-02-12

申请号：US12053679

申请日：2008-03-24

申请人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

发明人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L21/76245

摘要： A fabricating method for silicon on insulator is disclosed, and the fabricating method includes stripping the oxide and the nitride on the bottom surface of each of the trenches, forming a porous silicon on portions of the substrate by an anodizing process, spin coating a dielectric material to fill up the trenches and performing a thermal process to convert the porous silicon to an insulating layer.

摘要翻译： 公开了一种绝缘体硅的制造方法，其制造方法包括：剥离每个沟槽的底表面上的氧化物和氮化物，通过阳极氧化处理在衬底的部分上形成多孔硅，旋涂介电材料 填充沟槽并执行热处理以将多孔硅转化为绝缘层。

公开(公告)号：US20080316674A1

公开(公告)日：2008-12-25

申请号：US12000145

申请日：2007-12-10

申请人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

发明人： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC分类号： H01G4/06 ,  H01G9/00

CPC分类号： H01L28/91 ,  H01G4/252 ,  H01G4/33 ,  H01L27/10852

摘要： Capacitors and methods for fabricating the same are provided. An exemplary embodiment of a capacitor comprises a dielectric layer and a first conductive layer thereover. A supporting rib is embedded in the first conductive layer and extends along a first direction. A second conductive layer is embedded in the first conductive layer and extends along a second direction perpendicular with the first direction, wherein a portion of the second conductive layer forms across the supporting rib and is structurally supported by the supporting rib. A capacitor layer is formed between the first and second conductive layers to electrically insulate the first and second conductive layers.

摘要翻译： 提供了电容器及其制造方法。 电容器的示例性实施例包括电介质层和其上的第一导电层。 支撑肋嵌入在第一导电层中并且沿着第一方向延伸。 第二导电层被嵌入在第一导电层中并且沿着与第一方向垂直的第二方向延伸，其中第二导电层的一部分跨过支撑肋形成并且在结构上由支撑肋支撑。 在第一和第二导电层之间形成电容器层，以使第一和第二导电层电绝缘。

公开(公告)号：US06393210B1

公开(公告)日：2002-05-21

申请号：US09469146

申请日：1999-12-21

申请人： Hsiao-Che Wu

发明人： Hsiao-Che Wu

IPC分类号： F26B1900

CPC分类号： H01L21/67115

摘要： An apparatus for the rapid thermal processing of a semiconductor wafer is disclosed. The apparatus includes a preheat unit for preheating a gas composition, and a RTP reactor having a processing chamber and a heat source for heating the wafer. The processing chamber has a wafer holder, and a gas inlet and a gas outlet through which the preheated gas composition flows in and out of the processing chamber.

摘要翻译： 公开了一种用于半导体晶片快速热处理的装置。 该装置包括用于预热气体组合物的预热单元，以及具有用于加热晶片的处理室和热源的RTP反应器。 处理室具有晶片保持器，以及气体入口和气体出口，预热气体组合物通过该出口和气体出口流入和流出处理室。

公开(公告)号：US20080076241A1

公开(公告)日：2008-03-27

申请号：US11641131

申请日：2006-12-19

申请人： Tsung-Hsun Yang ,  Hsiao-Che Wu ,  Feng-Chun Chen ,  Chien-Hsun Pan

发明人： Tsung-Hsun Yang ,  Hsiao-Che Wu ,  Feng-Chun Chen ,  Chien-Hsun Pan

IPC分类号： H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/3211

摘要： A method for reducing stress between a conductive layer and a mask layer is provided. The method for reducing stress comprises a step of performing a plasma treatment with a nitrogen-containing gas to modify a surface of the conductive layer prior to the formation of the mask layer upon the surface. The method is useful for the manufacture of a gate, and the method for manufacturing the gate comprises the steps of providing a substrate; and sequentially depositing an oxide layer, a conductive layer, and a mask layer on the substrate to form a gate stack structure. The conductive layer is subjected to a surface plasma treatment with a nitrogen-containing gas prior to depositing the mask layer to modify its surface.

摘要翻译： 提供了一种用于减小导电层和掩模层之间的应力的方法。 减少应力的方法包括在表面形成掩模层之前，用含氮气体进行等离子体处理以改变导电层的表面的步骤。 该方法对于制造栅极是有用的，并且用于制造栅极的方法包括以下步骤：提供基板; 并在衬底上依次沉积氧化物层，导电层和掩模层以形成栅叠层结构。 在沉积掩模层以改变其表面之前，用含氮气体对导电层进行表面等离子体处理。

公开(公告)号：US20070210374A1

公开(公告)日：2007-09-13

申请号：US11308906

申请日：2006-05-25

申请人： Hsiao-Che Wu

发明人： Hsiao-Che Wu

IPC分类号： H01L31/00

CPC分类号： H01L29/7827 ,  H01L29/456 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666

摘要： A vertical-type surrounding gate semiconductor device is described. The semiconductor device comprises a pillar substrate, a collar oxide layer, a metal layer, a drain region, a ground line, a source region, a bit line, a word line, a gate and a gate dielectric layer. The ground line is formed in an opening of the pillar substrate and electrically connected to the pillar substrate, and covers the collar oxide layer and the metal layer. The drain region is formed on the top of the pillar substrate and in the upper portion of the opening. The gate is formed among the word line, the bit line and the pillar substrate. The gate dielectric layer is formed among the gate, the source region, the drain region, the bit line and the pillar substrate.

摘要翻译： 描述了垂直型周围栅极半导体器件。 该半导体器件包括柱状基底，环状氧化物层，金属层，漏极区域，接地线，源极区域，位线，字线，栅极和栅极电介质层。 接地线形成在支柱基板的开口部，与柱基板电连接，覆盖环状氧化物层和金属层。 漏极区域形成在支柱基板的顶部和开口的上部。 栅极形成在字线，位线和柱基板之间。 在栅极，源极区域，漏极区域，位线和柱状基板之间形成栅极电介质层。