公开(公告)号：US06580658B1

公开(公告)日：2003-06-17

申请号：US10065661

申请日：2002-11-07

申请人： Yu-Ming Hsu ,  Yen-Tai Lin ,  Chien-Hung Ho

发明人： Yu-Ming Hsu ,  Yen-Tai Lin ,  Chien-Hung Ho

IPC分类号： G11C800

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A word line driver includes an address decoder having a first circuit and a second circuit for selecting the word line, and a control end disposed between the first circuit and the second circuit. In addition, the word line driver has a level shift circuit for shifting a voltage level of the word line, and the level shift circuit has an input end connected to the second circuit of the address decoder. A method of driving a word line includes shifting a voltage level of the control end while turning on the second circuit so as to shift a voltage level of the input end of the level shift circuit, and shifting a voltage level of at least one of the first and second power supplies and using the second circuit to isolate the voltage level of the control end from the voltage level of the word line.

摘要翻译： 字线驱动器包括具有第一电路的地址解码器和用于选择字线的第二电路，以及设置在第一电路和第二电路之间的控制端。 此外，字线驱动器具有用于移位字线的电压电平的电平移位电路，并且电平移位电路具有连接到地址解码器的第二电路的输入端。 一种驱动字线的方法包括：在接通第二电路的同时移动控制端的电压电平，以便移位电平移位电路的输入端的电压电平，并移位至少一个 第一和第二电源，并使用第二电路将控制端的电压电平与字线的电压电平隔离开。

公开(公告)号：US06819620B2

公开(公告)日：2004-11-16

申请号：US10248495

申请日：2003-01-23

申请人： Yen-Tai Lin ,  Ching-Yuan Lin ,  Chien-Hung Ho

发明人： Yen-Tai Lin ,  Ching-Yuan Lin ,  Chien-Hung Ho

IPC分类号： G11C1134

CPC分类号： G11C16/30

摘要： A power supply used for providing a flash memory with an operating voltage has a plurality of memory blocks and a plurality of decoders corresponding to the memory blocks. Each memory block has a plurality of memory cells for storing binary data. Each decoder is used for selecting memory cells in the corresponding memory block. The power supply has at least three power sources for generating different voltages, and controls the power sources for making a voltage difference between a high voltage level and a low voltage level of the unselected decoder less than a voltage difference between a high voltage level and a low voltage level of the selected decoder.

摘要翻译： 用于提供具有工作电压的闪速存储器的电源具有多个存储块和对应于存储块的多个解码器。 每个存储块具有用于存储二进制数据的多个存储单元。 每个解码器用于选择相应存储块中的存储单元。 电源具有用于产生不同电压的至少三个电源，并且控制电源以使未选择的解码器的高电压电平和低电压电平之间的电压差小于高电压电平和高电压电平之间的电压差 所选解码器的低电压电平。

公开(公告)号：US06580645B1

公开(公告)日：2003-06-17

申请号：US10065660

申请日：2002-11-07

申请人： Yen-Tai Lin ,  Chien-Hung Ho

发明人： Yen-Tai Lin ,  Chien-Hung Ho

IPC分类号： G11C1600

CPC分类号： G11C16/10 ,  G11C2216/14

摘要： A page buffer for a flash memory has a power supply, a latch circuit, and a plurality of switches. Initially the switches are controlled for resetting a first terminal and a second terminal of the latch circuit to a respective predetermined voltage. If a memory cell is not to be programmed, the voltage levels of the first terminal and the second terminal remain unchanged when the power supply outputs a programming voltage. If the memory cell is to be programmed, the voltage levels of the first terminal and the second terminal are changed when the power supply outputs the programming voltage. Each of the first terminal and the second terminal will regain the predetermined voltage after the memory cell is completely programmed to store a predetermined binary digit.

摘要翻译： 闪存的页缓冲器具有电源，锁存电路和多个开关。 最初，开关被控制用于将锁存电路的第一端子和第二端子复位到相应的预定电压。 如果不编程存储单元，则当电源输出编程电压时，第一端子和第二端子的电压电平保持不变。 如果要对存储器单元进行编程，则当电源输出编程电压时，第一端子和第二端子的电压电平发生变化。 在存储器单元被完全编程以存储预定二进制数位之后，第一端子和第二端子中的每一个将重新获得预定电压。

公开(公告)号：US08591756B2

公开(公告)日：2013-11-26

申请号：US13309890

申请日：2011-12-02

申请人： Shih-Long Wei ,  Shen-Li Hsiao ,  Chien-Hung Ho

发明人： Shih-Long Wei ,  Shen-Li Hsiao ,  Chien-Hung Ho

IPC分类号： C23F1/00

CPC分类号： H01L21/4807 ,  H01L23/15 ,  H01L2924/0002 ,  Y10T428/24926 ,  Y10T428/31678 ,  H01L2924/00

摘要： A method of manufacturing a metallized ceramic substrate includes forming a metal layer on a ceramic substrate, and forming on the metal layer a resist having a first patterned resist opening and a second patterned resist opening for the metal layer to be exposed therefrom. A first width of the first patterned resist opening is greater than the thickness of the metal layer, and a second width of the second patterned resist opening is less than the thickness of the metal layer. A wet-etching process is conducted, to form in the first patterned resist opening a patterned metal layer opening and form in the second patterned resist opening a patterned metal layer dent. Therefore, an internal stress between the metal layer and the ceramic substrate is reduced, and the yield rate and reliability of the metallized ceramic substrate is increased.

摘要翻译： 金属化陶瓷基板的制造方法包括在陶瓷基板上形成金属层，在金属层上形成抗蚀剂，该抗蚀剂具有第一图案化抗蚀剂开口和第二图案化抗蚀剂开口，用于使金属层暴露于其中。 第一图案化抗蚀剂开口的第一宽度大于金属层的厚度，第二图案化抗蚀剂开口的第二宽度小于金属层的厚度。 进行湿蚀刻工艺，以在第一图案化的抗蚀剂开口中形成图案化的金属层开口，并在第二图案化的抗蚀剂开口中形成图案化的金属层凹陷。 因此，金属层与陶瓷基板之间的内应力降低，金属化陶瓷基板的成品率和可靠性提高。

公开(公告)号：US08590140B2

公开(公告)日：2013-11-26

申请号：US12873827

申请日：2010-09-01

申请人： Shih-Long Wei ,  Shen-Li Hsiao ,  Chien-Min Shao ,  Chien-Hung Ho

发明人： Shih-Long Wei ,  Shen-Li Hsiao ,  Chien-Min Shao ,  Chien-Hung Ho

IPC分类号： H01C17/00

CPC分类号： H01C17/07 ,  H01C7/003 ,  H01C17/006 ,  H01C17/065

摘要： A fabrication method of an alloy resistor includes: providing an alloy sheet having a plurality of openings spacing apart from each other and going through the alloy sheet and a plurality of alloy resistor units located between any two adjacent openings, wherein each of the alloy resistor units has an insulating cover area and a plurality of electrode ends on both sides of the insulating cover area; forming an insulating layer on a surface of the insulating cover area of the alloy resistor units by an electrodeposition coating process; cutting the alloy along a connecting portion, so as to obtain separated alloy resistor units; and forming a conductive adhesion material on the electrode ends of the alloy resistor units. An alloy resistor having an insulating layer with a smooth surface can be obtained by performing an electrodeposition coating process.

摘要翻译： 合金电阻器的制造方法包括：提供具有彼此间隔开并且穿过合金板的多个开口的合金片和位于任意两个相邻开口之间的多个合金电阻器单元，其中每个合金电阻器单元 绝缘覆盖区域和绝缘覆盖区域两侧的多个电极端部; 通过电沉积涂覆工艺在合金电阻器单元的绝缘覆盖区域的表面上形成绝缘层; 沿着连接部分切割合金，以获得分离的合金电阻器单元; 以及在合金电阻器单元的电极端上形成导电粘合材料。 通过进行电沉积涂布工艺，可以得到具有光滑表面的绝缘层的合金电阻体。

公开(公告)号：US07020036B2

公开(公告)日：2006-03-28

申请号：US10904381

申请日：2004-11-08

申请人： Chiun-Chi Shen ,  Chun-Hung Lu ,  Chien-Hung Ho

发明人： Chiun-Chi Shen ,  Chun-Hung Lu ,  Chien-Hung Ho

IPC分类号： G11C7/02

CPC分类号： G11C7/067 ,  G11C7/14 ,  G11C2207/063

摘要： A memory unit with sensing current stabilization includes: a memory cell; a reference cell for providing a reference current; a current mirror coupled to the memory cell and the reference cell for generating a differential current according to the reference current and a cell current of the memory cell; and a sense amplifier coupled to the current mirror for generating an output voltage according to the differential current.

摘要翻译： 具有感测电流稳定性的存储单元包括：存储单元; 用于提供参考电流的参考单元; 耦合到存储单元和参考单元的电流镜，用于根据参考电流和存储单元的单元电流产生差分电流; 以及耦合到电流镜的读出放大器，用于根据差分电流产生输出电压。

公开(公告)号：US06958597B1

公开(公告)日：2005-10-25

申请号：US10709470

申请日：2004-05-07

申请人： Hong-chin Lin ,  Po-Hsuan Huang ,  Chien-Hung Ho

发明人： Hong-chin Lin ,  Po-Hsuan Huang ,  Chien-Hung Ho

IPC分类号： G05F1/40 ,  G05F3/16 ,  G05F3/26 ,  G05F3/30

CPC分类号： G05F3/262 ,  G05F3/30 ,  Y10S323/907

摘要： Voltage generating apparatus includes a positive temperature coefficient current generating module, a negative temperature coefficient current generating module, a fine-tune current module and a voltage output module. The function of the positive temperature coefficient current generating module and the negative temperature coefficient current generating module, which take advantage of characteristics of MOS devices operated in the sub-threshold region, is to generate a stable current of positive temperature coefficient and a stable current of negative temperature coefficient, respectively. The current fine-tune module increases or decreases output current of the negative temperature coefficient current generating module. The voltage output module sums two output currents of the positive temperature coefficient current generating module and the negative temperature coefficient current generating module and transforms the total current into output voltage that is stable under temperature and process variation.

摘要翻译： 电压产生装置包括正温度系数电流产生模块，负温度系数电流产生模块，微调电流模块和电压输出模块。 利用在亚阈值区域工作的MOS器件的特性的正温度系数电流发生模块和负温度系数电流发生模块的功能是产生正温度系数和稳定电流的稳定电流 负温度系数。 当前微调模块增加或减少负温度系数电流发生模块的输出电流。 电压输出模块将正温度系数电流发生模块和负温度系数电流发生模块的两个输出电流相加，并将总电流转换为在温度和工艺变化下稳定的输出电压。

公开(公告)号：US20130098867A1

公开(公告)日：2013-04-25

申请号：US13314392

申请日：2011-12-08

申请人： Shih-Long Wei ,  Shen-Li Hsiao ,  Chien-Hung Ho

发明人： Shih-Long Wei ,  Shen-Li Hsiao ,  Chien-Hung Ho

IPC分类号： C23F1/00

CPC分类号： C04B37/026 ,  C04B2237/123 ,  C04B2237/125 ,  C04B2237/127 ,  C04B2237/343 ,  C04B2237/365 ,  C04B2237/366 ,  C04B2237/402 ,  C04B2237/406 ,  C04B2237/407 ,  C04B2237/592 ,  C04B2237/86

摘要： A method of selective metallization on a ceramic substrate includes selectively forming an active brazing material on a predetermined area of a surface of a ceramic substrate, attaching the metal layer to the ceramic substrate with the active brazing material, performing a brazing process on the active brazing material, forming an etching stop layer on the metal layer and performing an etching process, and removing the etching stop layer. The method can be applied to a severe environment, and the conchoidal fracture between the ceramic substrate and the metal layer can also be avoided. The present invention not only simplifies the process but also improves the product yield.

摘要翻译： 在陶瓷基板上选择性金属化的方法包括在陶瓷基板的表面的预定区域选择性地形成活性钎焊材料，用活性钎焊材料将金属层附着到陶瓷基体上，对活性钎焊进行钎焊处理 在金属层上形成蚀刻停止层，进行蚀刻处理，除去蚀刻停止层。 该方法可以应用于恶劣环境，也可以避免陶瓷基板与金属层之间的凹凸断裂。 本发明不仅简化了工艺，而且提高了产品的产率。

公开(公告)号：US20080205115A1

公开(公告)日：2008-08-28

申请号：US11836362

申请日：2007-08-09

申请人： Chien-Hung Ho ,  Yu WU

发明人： Chien-Hung Ho ,  Yu WU

IPC分类号： G11C17/00

CPC分类号： G11C17/18 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/26

摘要： A trimming apparatus including a switch transistor and a one-time programming (OTP) memory component is provided. The switch transistor has a first source/drain terminal connected to a first bias voltage, a gate terminal used for receiving a switch signal, and a second source/drain terminal connected to a first source/drain terminal of the OTP memory component. When the trimming apparatus provided by the present invention intends to perform trimming for an integrated circuit, the switch transistor is conducted to program the OTP memory component.

摘要翻译： 提供了一种包括开关晶体管和一次性编程（OTP）存储器组件的修整装置。 开关晶体管具有连接到第一偏置电压的第一源极/漏极端子，用于接收开关信号的栅极端子以及连接到OTP存储器组件的第一源极/漏极端子的第二源极/漏极端子。 当本发明提供的修剪装置意图对集成电路进行修整时，导通开关晶体管对OTP存储器部件进行编程。

公开(公告)号：US20050151580A1

公开(公告)日：2005-07-14

申请号：US10707786

申请日：2004-01-12

申请人： Hong-chin Lin ,  Ming-Chih Hsieh ,  Jain-Hao Lu ,  Chien-Hung Ho

发明人： Hong-chin Lin ,  Ming-Chih Hsieh ,  Jain-Hao Lu ,  Chien-Hung Ho

IPC分类号： G05F1/10 ,  G05F3/02 ,  H02M3/07

CPC分类号： H02M3/073 ,  H02M2003/075 ,  H02M2003/077

摘要： A four-phase dual pumping circuit has a number of stages according to the required output voltage based on an input voltage. Each stage has a first pumping unit and a second pumping unit that are mirror and identical to each other and electrically coupled to each other. The dual pumping circuit is controlled by four-phase clocks which are made from one pair of out of phase clocks. The transistors of the dual pumping circuit have special substrate connection to minimize body effects. The four-phase dual pumping circuit uses NMOSFETS for negative pumping and PMOSFETS for positive pumping.

摘要翻译： 四相双泵浦电路根据输入电压根据所需的输出电压具有多个级。 每个级具有彼此镜像并相同并且彼此电耦合的第一泵送单元和第二泵送单元。 双泵电路由四相时钟控制，这四个时钟由一对异相时钟产生。 双泵浦电路的晶体管具有特殊的基板连接以最小化身体效应。 四相双泵浦电路使用NMOSFETS进行负泵浦和PMOSFETS进行正泵浦。