-
公开(公告)号：US06492712B1
公开(公告)日：2002-12-10
申请号：US09597077
申请日：2000-06-20
IPC分类号： H01L21316
CPC分类号： C30B29/06 , C30B33/005 , H01L21/02238 , H01L21/02255 , H01L21/28185 , H01L21/28211 , H01L21/28273 , H01L21/31662 , H01L29/513 , H01L29/518
摘要： An oxide for use in integrated circuits is substantially stress-free both in the bulk and at the interface between the substrate and the oxide. The interface is planar and has a low interface trap density (Nit). The oxide has a low defect density and may have a thickness of less than 1.5 nm or less.
摘要翻译： 用于集成电路的氧化物在本体和衬底与氧化物之间的界面处基本上是无应力的。 界面是平面的，并且具有低的界面陷阱密度（Nit）。 氧化物的缺陷密度低，可以具有小于1.5nm以下的厚度。
-
公开(公告)号：US06291848B1
公开(公告)日：2001-09-18
申请号：US09364767
申请日：1999-07-30
申请人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
发明人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L27108
CPC分类号： H01L21/76838 , H01L27/10817 , H01L27/10852 , H01L28/60
摘要： An integrated circuit capacitor includes a substrate, a first dielectric layer adjacent the substrate and having a first trench therein, and a first metal plug extending upwardly into the first trench. An interconnection line overlies the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. A second dielectric layer is on the interconnection line and has a second trench therein. A second metal plug extends upwardly into the second trench. More particularly, the second metal plug includes a body portion extending upwardly into the second trench, and anchor portions connected to the body portion and engaging the anchoring recesses to anchor the second metal plug to the interconnection line. Because the second metal plug is anchored, a depth of the second trench can be greater without the metal plug becoming loose and separating from the underlying interconnection line.
摘要翻译： 集成电路电容器包括衬底，与衬底相邻并且在其中具有第一沟槽的第一电介质层和向上延伸到第一沟槽中的第一金属插塞。 互连线覆盖在第一沟槽上并接触第一金属插塞以在第一金属插塞的相对侧上限定锚定凹槽。 第二介电层位于互连线上并且在其中具有第二沟槽。 第二金属插头向上延伸到第二沟槽中。 更具体地，第二金属插头包括向上延伸到第二沟槽中的主体部分，以及连接到主体部分并且与固定凹部接合并将第二金属插头固定到互连线的锚定部分。 由于第二金属插塞被锚固，所以第二沟槽的深度可以更大，而不会使金属插头松动并与下面的互连线分离。
-
3.发明授权
公开(公告)号：US6103586A
公开(公告)日：2000-08-15
申请号：US364025
申请日：1999-07-30
申请人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
发明人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/768 , H01L27/108 , H01L21/20
CPC分类号： H01L28/60 , H01L21/76838 , H01L21/76895
摘要： A method for making an integrated circuit capacitor includes forming a first dielectric layer adjacent a substrate, forming a first opening in the first dielectric layer, filling the first opening with a conductive material to define a first metal plug, and forming a trench in the first dielectric layer adjacent the first metal plug. An interconnection line lines the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. The method further includes forming a second dielectric layer on the interconnection line, forming a second opening in the second dielectric layer, and filling the second opening with a conductive metal to define a second metal plug having a body portion and anchor portions extending downward from the body portion for engaging the anchoring recesses to anchor the second metal plug. A second trench is formed in the second dielectric layer adjacent the second metal plug, and is aligned with the first trench. Because the second metal plug is anchored, a depth of the second trench can be greater without the metal plug becoming loose and separating from the underlying interconnection line. The electrodes and dielectric layers of the capacitor are formed so that they line the second trench.
摘要翻译： 一种制造集成电路电容器的方法包括：在基片附近形成第一电介质层，在第一电介质层中形成第一开口，用导电材料填充第一开口以限定第一金属插塞，并在第一电介质层中形成沟槽 电介质层邻近第一金属插头。 互连线对准第一沟槽并接触第一金属插塞以在第一金属插塞的相对侧上限定锚定凹槽。 所述方法还包括在所述互连线上形成第二电介质层，在所述第二电介质层中形成第二开口，并用导电金属填充所述第二开口，以限定第二金属插塞，所述第二金属插塞具有主体部分和从所述第二介质层向下延伸的固定部分 主体部分，用于接合所述锚定凹部以锚定所述第二金属插塞。 在与第二金属插塞相邻的第二电介质层中形成第二沟槽，并且与第一沟槽对准。 由于第二金属插塞被锚固，所以第二沟槽的深度可以更大，而不会使金属插头松动并与下面的互连线分离。 电容器的电极和电介质层形成为使得它们与第二沟槽对齐。
-
4.发明授权Method of making a graded grown, high quality oxide layer for a semiconductor device 有权制造用于半导体器件的分级生长的高质量氧化物层的方法公开(公告)号：US06541394B1
公开(公告)日：2003-04-01
申请号：US09481992
申请日：2000-01-11
IPC分类号： H01L2131
CPC分类号： H01L21/28202 , C30B29/06 , C30B33/005 , H01L21/02238 , H01L21/02255 , H01L21/02304 , H01L21/02312 , H01L21/28185 , H01L21/28211 , H01L21/28273 , H01L21/31604 , H01L21/31612 , H01L21/31662 , H01L21/3185 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for making an oxide layer on a silicon substrate produces an oxide layer including graded portions with greatly reduced stress. The method includes growing a first oxide portion over a substrate by upwardly ramping the substrate to a first temperature lower than a SiO2 viscoelastic temperature. Thereafter a second oxide portion is grown between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the SiO2 viscoelastic temperature. The second oxide portion may have a thickness in a range of about 25 to 50% of a total thickness of the graded oxide layer.
摘要翻译： 在硅衬底上制造氧化物层的方法产生包括具有大大降低的应力的渐变部分的氧化物层。 该方法包括通过将衬底向上倾斜到低于SiO 2粘弹性温度的第一温度而在衬底上生长第一氧化物部分。 此后，在高于SiO 2粘弹性温度的第二温度下，通过将硅衬底暴露于氧化环境，在第一氧化物部分和硅衬底之间生长第二氧化物部分。 第二氧化物部分可以具有梯度氧化物层的总厚度的约25至50％范围内的厚度。
-
5.发明授权公开(公告)号：US07148153B2
公开(公告)日：2006-12-12
申请号：US10316386
申请日：2002-12-11
IPC分类号： H01L21/31
CPC分类号： H01L21/28185 , H01L21/28211 , H01L29/513 , H01L29/517
摘要： A process for forming an oxide layer includes forming a first oxide portion over a substrate at a temperature below a threshold temperature. A second oxide portion is formed under the first oxide portion at a temperature above the threshold temperature. The substrate is illustratively oxidizable silicon and the threshold temperature is the viscoelastic temperature of silicon dioxide.
-
6.发明授权TWO-STEP OXIDATION PROCESS FOR OXIDIZING A SILICON SUBSTRATE WHEREIN THE FIRST STEP IS CARRIED OUT AT A TEMPERATURE BELOW THE VISCOELASTIC TEMPERATURE OF SILICON DIOXIDE AND THE SECOND STEP IS CARRIED OUT AT A TEMPERATURE ABOVE THE VISCOELASTIC TEMPERATURE 有权用于氧化硅基板的两步氧化工艺，其中第一步在下文所述的温度下，在二氧化硅的粘弹性温度下进行，第二步在温度上保持在粘弹性温度公开(公告)号：US06551946B1
公开(公告)日：2003-04-22
申请号：US09597076
申请日：2000-06-20
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , C30B29/06 , C30B33/005 , H01L21/02238 , H01L21/02255 , H01L21/28202 , H01L21/28211 , H01L21/28273 , H01L21/31604 , H01L21/31612 , H01L21/31662 , H01L21/3185 , H01L29/513
摘要： A process for forming an oxide layer includes forming a first oxide portion over a substrate at a temperature below a threshold temperature. A second oxide portion is formed under the first oxide portion at a temperature above the threshold temperature. The substrate is illustratively oxidizable silicon and the threshold temperature is the viscoelastic temperature of silicon dioxide.
摘要翻译： 形成氧化物层的方法包括在低于阈值温度的温度下在衬底上形成第一氧化物部分。 在高于阈值温度的温度下，在第一氧化物部分的下面形成第二氧化物部分。 衬底是可氧化的硅，阈值温度是二氧化硅的粘弹性温度。
-
公开(公告)号：US06358790B1
公开(公告)日：2002-03-19
申请号：US09250501
申请日：1999-02-16
IPC分类号： H01L218234
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/32136 , H01L27/1085 , H01L28/40 , H01L28/75 , H01L28/90
摘要： The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a plug, planarizing the substrate, patterning the substrate to expose the first material, forming an electrode material layer over the substrate, and patterning the electrode material layer, whereby the first material is substantially encapsulated by the electrode material layer.
摘要翻译： 本发明提供一种制造电容器的方法，包括以下步骤：在衬底中形成沟槽，在沟槽中形成从由钛和氮化钛组成的组中选择的第一材料的层，用导电材料填充沟槽 以形成插头，使衬底平坦化，图案化衬底以露出第一材料，在衬底上形成电极材料层，以及图案化电极材料层，由此第一材料基本上被电极材料层封装。
-
公开(公告)号：US06331484B1
公开(公告)日：2001-12-18
申请号：US09519193
申请日：2000-03-06
IPC分类号： H01L214763
CPC分类号： H01L21/76864 , H01L21/76807 , H01L21/76841 , H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A titanium-tantalum barrier layer film for use in conjunction with an interconnect film such as copper and a method for forming the same provides a relatively titanium rich/tantalum deficient portion adjacent the interface it forms with a dielectric film and a relatively tantalum rich/titanium deficient portion adjacent the interface it forms with a conductive interconnect film formed over the barrier layer film. The titanium rich/tantalum deficient portion provides good adhesion to the dielectric film and the tantalum rich/titanium deficient portion forms a hetero-epitaxial interface with the interconnect film and suppresses the formation of inter-metallic compounds. A single titanium-tantalum film having a composition gradient from top-to-bottom may be formed using various techniques including PVD, CVD, sputter deposition using a sputtering target of homogeneous composition, and sputter deposition using multiple sputtering targets. A composite titanium-tantalum film consists of two separately formed films.
摘要翻译： 用于与诸如铜的互连膜一起使用的钛 - 钽阻挡层膜及其形成方法提供了与其形成的界面相邻的富钛/钽缺陷部分，其与介电膜和相对富钽/钛 与其形成的界面相邻的缺陷部分与在阻挡层膜上形成的导电互连膜形成。 富钛/钽缺陷部分对电介质膜提供良好的粘附性，并且富钽/钛缺陷部分与互连膜形成异质外延界面并抑制金属间化合物的形成。 可以使用包括PVD，CVD，使用均匀组合物的溅射靶的溅射沉积以及使用多个溅射靶的溅射沉积的各种技术来形成具有从顶部到底部的组成梯度的单个钛 - 钽膜。 复合钛 - 钽薄膜由两个单独形成的薄膜组成。
-
公开(公告)号：US06319837B1
公开(公告)日：2001-11-20
申请号：US09606833
申请日：2000-06-29
IPC分类号： H01L2100
CPC分类号： H01L21/7684
摘要： The present invention includes a method for reducing dishing of an integrated circuit interconnect, comprising the steps of providing excess interconnect material above a damascene feature in a substrate and planarizing the substrate and interconnect material to obtain an interconnect in the substrate.
摘要翻译： 本发明包括一种用于减少集成电路互连的凹陷的方法，包括以下步骤：在衬底上的镶嵌特征之上提供过量的互连材料，并平坦化衬底和互连材料以获得衬底中的互连。
-
10.发明授权Colloidal suspension of abrasive particles containing magnesium as CMP slurry 有权含有镁的磨料颗粒的胶体悬浮液作为CMP浆料公开(公告)号：US06319095B1
公开(公告)日：2001-11-20
申请号：US09521768
申请日：2000-03-09
IPC分类号： B24B100
CPC分类号： C09K3/1463 , B24B37/044 , C09G1/02
摘要： An improved colloidal slurry for chemical mechanical polishing and methods of polishing using the improved colloidal slurry.
摘要翻译： 用于化学机械抛光的改进的胶体浆料和使用改进的胶体浆料的抛光方法。
-
-
-
-
-
-
-
-
-
搜索结果
65 条记录 (耗时 0.2 秒)
