公开(公告)号：US07518173B2

公开(公告)日：2009-04-14

申请号：US11129490

申请日：2005-05-16

申请人： Yukinobu Hikosaka ,  Mitsushi Fujiki ,  Kazutoshi Izumi ,  Naoya Sashida ,  Aki Dote

发明人： Yukinobu Hikosaka ,  Mitsushi Fujiki ,  Kazutoshi Izumi ,  Naoya Sashida ,  Aki Dote

IPC分类号： H01L29/41 ,  H01L29/43

CPC分类号： H01L27/11507 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/7687 ,  H01L27/11502 ,  H01L28/57

摘要： A semiconductor device includes: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate and having an insulated gate and source/drain regions on both sides of the insulated gate; a ferroelectric capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode; a metal film formed on the upper electrode and having a thickness of a half of or thinner than a thickness of the upper electrode; an interlayer insulating film burying the ferroelectric capacitor and the metal film; a conductive plug formed through the interlayer insulating film, reaching the metal film and including a conductive glue film and a tungsten body; and an aluminum wiring formed on the interlayer insulating film and connected to the conductive plug. A new problem near an upper electrode contact is solved which may otherwise be caused by adopting a W plug over the F capacitor.

摘要翻译： 半导体器件包括：半导体衬底; 形成在所述半导体衬底中并且在所述绝缘栅极的两侧具有绝缘栅极和源极/漏极区域的MOS晶体管; 形成在半导体衬底上并具有下电极，铁电层和上电极的铁电电容器; 形成在上电极上并具有比上电极的厚度的一半或更薄的厚度的金属膜; 埋置铁电电容器和金属膜的层间绝缘膜; 通过层间绝缘膜形成的导电插塞，到达金属膜并且包括导电胶膜和钨体; 以及形成在层间绝缘膜上并连接到导电插塞的铝布线。 解决了上电极接触附近的新问题，否则可能是通过在F电容器上采用W插头引起的。

公开(公告)号：US20060157762A1

公开(公告)日：2006-07-20

申请号：US11129490

申请日：2005-05-16

申请人： Yukinobu Hikosaka ,  Mitsushi Fujiki ,  Kazutoshi Izumi ,  Naoya Sashida ,  Aki Dote

发明人： Yukinobu Hikosaka ,  Mitsushi Fujiki ,  Kazutoshi Izumi ,  Naoya Sashida ,  Aki Dote

IPC分类号： H01L29/94

CPC分类号： H01L27/11507 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/7687 ,  H01L27/11502 ,  H01L28/57

摘要： A semiconductor device includes: a semiconductor substrate; a MOS transistor formed in the semiconductor substrate and having an insulated gate and source/drain regions on both sides of the insulated gate; a ferroelectric capacitor formed above the semiconductor substrate and having a lower electrode, a ferroelectric layer and an upper electrode; a metal film formed on the upper electrode and having a thickness of a half of or thinner than a thickness of the upper electrode; an interlayer insulating film burying the ferroelectric capacitor and the metal film; a conductive plug formed through the interlayer insulating film, reaching the metal film and including a conductive glue film and a tungsten body; and an aluminum wiring formed on the interlayer insulating film and connected to the conductive plug. A new problem near an upper electrode contact is solved which may otherwise be caused by adopting a W plug over the F capacitor.

公开(公告)号：US06509593B2

公开(公告)日：2003-01-21

申请号：US09750069

申请日：2000-12-29

申请人： Kenichi Inoue ,  Yoshinori Obata ,  Takeyasu Saito ,  Kaoru Saigoh ,  Naoya Sashida ,  Koji Tani ,  Jirou Miura ,  Tatsuya Yokota ,  Satoru Mihara ,  Yukinobu Hikosaka ,  Yasutaka Ozaki

发明人： Kenichi Inoue ,  Yoshinori Obata ,  Takeyasu Saito ,  Kaoru Saigoh ,  Naoya Sashida ,  Koji Tani ,  Jirou Miura ,  Tatsuya Yokota ,  Satoru Mihara ,  Yukinobu Hikosaka ,  Yasutaka Ozaki

IPC分类号： H01L2976

CPC分类号： H01L27/11502 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L27/11507 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into the contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.

摘要翻译： 通过在绝缘膜上形成接触孔而形成的半导体器件，其通过相同的步骤在电容器的下电极上覆盖MOSFET的源极/漏极和存储单元区域中的电容器，然后将插头填充到触点中 孔，然后在电容器的上电极上形成接触孔。 因此，可以提供具有铁电电容器的半导体器件，其能够通过抑制在晶体管上形成的电容器的损坏来简化与电容器的上部电极和下部电极的各个布线连接结构。

公开(公告)号：US06913970B2

公开(公告)日：2005-07-05

申请号：US10303752

申请日：2002-11-26

申请人： Kenichi Inoue ,  Yoshinori Obata ,  Takeyasu Saito ,  Kaoru Saigoh ,  Naoya Sashida ,  Koji Tani ,  Jirou Miura ,  Tatsuya Yokota ,  Satoru Mihara ,  Yukinobu Hikosaka ,  Yasutaka Ozaki

发明人： Kenichi Inoue ,  Yoshinori Obata ,  Takeyasu Saito ,  Kaoru Saigoh ,  Naoya Sashida ,  Koji Tani ,  Jirou Miura ,  Tatsuya Yokota ,  Satoru Mihara ,  Yukinobu Hikosaka ,  Yasutaka Ozaki

IPC分类号： H01L23/522 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L21/20

CPC分类号： H01L27/11502 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L27/11507 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.

摘要翻译： 通过在绝缘膜上形成接触孔而形成的半导体器件，其通过相同的步骤在电容器的下电极上覆盖MOSFET的源/漏和存储单元区域中的电容器，然后将插头填充到接触孔 ，然后在电容器的上电极上形成接触孔。 因此，可以提供具有铁电电容器的半导体器件，其能够通过抑制在晶体管上形成的电容器的损坏来简化与电容器的上部电极和下部电极的各个布线连接结构。

公开(公告)号：US20070058416A1

公开(公告)日：2007-03-15

申请号：US11593018

申请日：2006-11-06

申请人： Yukinobu Hikosaka ,  Tomohiro Takamatsu ,  Yoshinori Obata

发明人： Yukinobu Hikosaka ,  Tomohiro Takamatsu ,  Yoshinori Obata

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C29/50 ,  G11C2029/5002

摘要： A method for inspecting a semiconductor memory having nonvolatile memory cells using ferroelectric capacitors is disclosed which comprises, after shelf-aging the ferroelectric capacitor in a first polarized state, the steps of: (a) writing a second polarized state opposite to the first polarized state; (b) shelf-aging the ferroelectric capacitor in the second polarized state; and (c) reading the second polarized state. The temperature or voltage in the step (a) is lower than the temperature or voltage in the step (c). This method for inspecting a semiconductor memory enables to evaluate the imprint characteristics in a short time.

摘要翻译： 公开了一种利用铁电电容器检测具有非易失性存储单元的半导体存储器的方法，该方法包括：在第一极化状态下对强电介质电容器进行保存老化之后，步骤：（a）写入与第一极化状态相反的第二极化状态 ; （b）在第二极化状态下老化铁电电容器; 和（c）读取第二极化状态。 步骤（a）中的温度或电压低于步骤（c）中的温度或电压。 这种用于检查半导体存储器的方法能够在短时间内评估印痕特性。

公开(公告)号：US06710422B2

公开(公告)日：2004-03-23

申请号：US10212092

申请日：2002-08-06

申请人： Yukinobu Hikosaka ,  Akio Itoh ,  Kazuaki Takai ,  Takeyasu Saito

发明人： Yukinobu Hikosaka ,  Akio Itoh ,  Kazuaki Takai ,  Takeyasu Saito

IPC分类号： H01L2972

CPC分类号： H01L27/11509 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/11507 ,  H01L28/40

摘要： A semiconductor device having conductive plug for connecting capacitor and conductive pattern, comprises first and second impurity diffusion regions formed in a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a first hole formed in the first insulating film on the first impurity diffusion region, a first conductive plug formed in the first hole and made of a metal film, a second hole formed in the first insulating film on the second impurity diffusion region, a second conductive plug formed in the second hole and made of conductive material that is hard to be oxidized rather than the metal film, and a capacitor that consists of a lower electrode connected to an upper surface of the second conductive plug, a dielectric film, and an upper electrode.

摘要翻译： 一种具有用于连接电容器和导电图案的导电插头的半导体器件，包括形成在半导体衬底中的第一和第二杂质扩散区域，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的第一杂质扩散部分上的第一孔 形成在第一孔中并由金属膜制成的第一导电插塞，形成在第二杂质扩散区域上的第一绝缘膜中的第二孔，形成在第二孔中并由导电材料制成的第二导电插塞， 难以被氧化而不是金属膜，以及电容器，其由连接到第二导电插塞的上表面的下电极，电介质膜和上电极组成。

公开(公告)号：US06706540B2

公开(公告)日：2004-03-16

申请号：US10361585

申请日：2003-02-11

申请人： Yukinobu Hikosaka ,  Yasutaka Ozaki ,  Kazuaki Takai

发明人： Yukinobu Hikosaka ,  Yasutaka Ozaki ,  Kazuaki Takai

IPC分类号： H01L2100

CPC分类号： H01L27/11502 ,  H01L27/10811 ,  H01L27/10894 ,  H01L27/11507 ,  H01L28/55

摘要： There is provided a semiconductor device which includes a capacitor including a lower electrode, a dielectric film, and an upper electrode, a first protection film formed on the capacitor, a first wiring formed on the first protection film, a first insulating film formed on the first wiring, a second wiring formed on the first insulating film, a second insulating film formed on the second wiring, and at least one of a second protection film formed between the first insulating film and the first wiring to cover at least the capacitor and a third protection film formed on the second insulating film to cover the capacitor and set to an earth potential. Accordingly, the degradation of the ferroelectric capacitor formed under the multi-layered wiring structure can be suppressed.

摘要翻译： 提供一种半导体器件，其包括具有下电极，电介质膜和上电极的电容器，形成在电容器上的第一保护膜，形成在第一保护膜上的第一布线，形成在第一保护膜上的第一绝缘膜 第一布线，形成在第一绝缘膜上的第二布线，形成在第二布线上的第二绝缘膜，以及形成在第一绝缘膜和第一布线之间的至少一个覆盖至少电容器的第二保护膜，以及 第三保护膜形成在第二绝缘膜上以覆盖电容器并设定为地电位。 因此，可以抑制在多层布线结构下形成的铁电电容器的劣化。

公开(公告)号：US07338815B2

公开(公告)日：2008-03-04

申请号：US11235362

申请日：2005-09-27

申请人： Yukinobu Hikosaka ,  Hirotoshi Tachibana

发明人： Yukinobu Hikosaka ,  Hirotoshi Tachibana

IPC分类号： H01L21/00 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8244 ,  H01L21/20

CPC分类号： H01L21/28518 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： A semiconductor device manufacturing method, includes a step of forming refractory metal silicide layers 13a to 13c in a partial area of a semiconductor substrate 10, a step of forming an interlayer insulating film 21 on the refractory metal silicide layers 13a to 13c, a step of forming a first conductive film 31, a ferroelectric film 32, and a second conductive film 33 in sequence on the interlayer insulating film 21, a step of forming a capacitor Q consisting of a lower electrode 31a, a capacitor dielectric film 32a, and an upper electrode 33a by patterning the first conductive film 33, the ferroelectric film 32, and the second conductive film 31, and a step of performing an annealing for an annealing time to suppress a agglomeration area of the refractory metal silicide layers 13a to 13c within an upper limit area.

摘要翻译： 一种半导体器件制造方法，包括在半导体衬底10的局部区域中形成难熔金属硅化物层13a至13c的步骤，在难熔金属硅化物层13a至13c上形成层间绝缘膜21的步骤 ，在层间绝缘膜21上依次形成第一导电膜31，铁电体膜32和第二导电膜33的工序，形成由下部电极31a，电容电介质膜 32a，以及通过对第一导电膜33，强电介质膜32和第二导电膜31进行图案化的上部电极33a，以及对退火时间进行退火以抑制难熔金属硅化物的凝聚面积的步骤 层13a至13c在上限区域内。

公开(公告)号：US07221015B2

公开(公告)日：2007-05-22

申请号：US10388596

申请日：2003-03-17

申请人： Takashi Ando ,  Jiro Miura ,  Yukinobu Hikosaka ,  Akio Itoh ,  Junichi Watanabe ,  Kenkichi Suezawa

发明人： Takashi Ando ,  Jiro Miura ,  Yukinobu Hikosaka ,  Akio Itoh ,  Junichi Watanabe ,  Kenkichi Suezawa

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： There are contained first and second conductive plugs formed in first insulating layer, an island-like oxygen-barrier metal layer for covering the first conductive plug, an oxidation-preventing insulating layer formed on the first insulating layer to cover side surfaces of the oxygen-barrier metal layer, a capacitor having a lower electrode formed on the oxygen-barrier metal layer and the oxidation-preventing insulating layer, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, a second insulating layer for covering the capacitor and the oxidation-preventing insulating layer, a third hole formed in respective layers from the second insulating layer to the oxidation-preventing insulating layer on the second conductive plug, and a third conductive plug formed in the third hole and connected to the second conductive plug.

摘要翻译： 存在形成在第一绝缘层中的第一和第二导电插塞，用于覆盖第一导电插塞的岛状氧阻隔金属层，形成在第一绝缘层上的氧化防止绝缘层，以覆盖氧 - 阻挡金属层，形成在氧阻隔金属层上的下电极的电容器和防氧化绝缘层，形成在下电极上的电介质层和形成在电介质层上的上电极，第二绝缘层， 覆盖电容器和防氧化绝缘层，形成在第二绝缘层到第二导电插塞上的防氧化绝缘层的各层中的第三孔和形成在第三孔中并连接到第三导电插塞的第三导电插塞 第二导电插头。

公开(公告)号：US20060281248A1

公开(公告)日：2006-12-14

申请号：US11235362

申请日：2005-09-27

申请人： Yukinobu Hikosaka ,  Hirotoshi Tachibana

发明人： Yukinobu Hikosaka ,  Hirotoshi Tachibana

IPC分类号： H01L21/8244

CPC分类号： H01L21/28518 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： A semiconductor device manufacturing method, includes a step of forming refractory metal silicide layers 13a to 13c in a partial area of a semiconductor substrate 10, a step of forming an interlayer insulating film 21 on the refractory metal silicide layers 13a to 13c, a step of forming a first conductive film 31, a ferroelectric film 32, and a second conductive film 33 in sequence on the interlayer insulating film 21, a step of forming a capacitor Q consisting of a lower electrode 31a, a capacitor dielectric film 32a, and an upper electrode 33a by patterning the first conductive film 33, the ferroelectric film 32, and the second conductive film 31, and a step of performing an annealing for an annealing time to suppress a agglomeration area of the refractory metal silicide layers 13a to 13c within an upper limit area.

摘要翻译： 一种半导体器件制造方法，包括在半导体衬底10的局部区域中形成难熔金属硅化物层13a至13c的步骤，在难熔金属硅化物层13a至13c上形成层间绝缘膜21的步骤 ，在层间绝缘膜21上依次形成第一导电膜31，铁电体膜32和第二导电膜33的工序，形成由下部电极31a，电容电介质膜 32a，以及通过对第一导电膜33，强电介质膜32和第二导电膜31进行图案化的上部电极33a，以及对退火时间进行退火以抑制难熔金属硅化物的凝聚面积的步骤 层13a至13c在上限区域内。