公开(公告)号：US06559834B1

公开(公告)日：2003-05-06

申请号：US09654285

申请日：2000-09-01

申请人： Yukio Murakami ,  Shunsuke Hirano ,  Keiichi Minakuchi

发明人： Yukio Murakami ,  Shunsuke Hirano ,  Keiichi Minakuchi

IPC分类号： G09G510

CPC分类号： G06F3/045

摘要： A touch panel is constructed of a top sheet member having a resistive membrane on its inner surface and a base sheet member having a resistive membrane on its inner surface, the top and base sheet members facing each other with dot spacers being located in between. The top sheet member is formed by laminating a bulge-resistant film, a polarizing plate, a quarter wavelength plate, and a light isotropic film in this order from above. A PET film which is not heat-treated so as to have a higher thermal contraction rate than the other members of the top sheet member underneath such as the polarizing plate, is used as the bulge-resistant film. Since the bulge-resistant film contracts more than the polarizing plate under a high ambient temperature, after the ambient temperature returns to normal, the bulge-resistant film does not become slack against the polarizing plate. Accordingly, the top sheet member can be kept from bulging outward.

摘要翻译： 触摸面板由在其内表面上具有电阻膜的顶片构件和在其内表面上具有电阻膜的基片构件构成，顶片和基片构件彼此面对，点间隔物位于其间。 通过从上方按顺序层叠防胀薄膜，偏振板，四分之一波长板和光各向同性膜而形成顶片部件。 作为防爆薄膜，使用未经热处理以具有比偏振片下方的顶片部件的其他部件高的热收缩率的PET膜。 由于耐高温膜在高环境温度下比偏振片收缩多，所以在环境温度恢复正常之后，防爆膜不会偏离偏振片。 因此，可以将顶片部件保持不向外凸出。

公开(公告)号：US06572941B1

公开(公告)日：2003-06-03

申请号：US09574104

申请日：2000-05-18

申请人： Yukio Murakami ,  Shunsuke Hirano

发明人： Yukio Murakami ,  Shunsuke Hirano

IPC分类号： G09G500

CPC分类号： G06F3/045 ,  Y10T428/24777 ,  Y10T428/24851 ,  Y10T428/24942 ,  Y10T428/31855

摘要： A touch panel is constructed of a top sheet member having a resistive membrane on its inner surface and a base sheet member having a resistive membrane on its inner surface, the top and base sheet members facing each other with dot spacers being located in between. The top sheet member is formed by laminating a PET film, a polarizing film, a ¼&lgr; retardation film, and a light isotropic film in this order from its outer surface. The PET film has a thermal expansion coefficient lower than the other films underneath, such as the polarizing film. Accordingly, the PET film serves to keep the other films of the top sheet member from bulging outward when the temperature rises.

摘要翻译： 触摸面板由在其内表面上具有电阻膜的顶片构件和在其内表面上具有电阻膜的基片构件构成，顶片和基片构件彼此面对，点间隔物位于其间。 顶片部件通过从其外表面依次层压PET膜，偏振膜，¼延伸膜和光各向同性膜而形成。 PET膜的热膨胀系数低于其它薄膜，如偏光膜。 因此，当温度升高时，PET膜用于保持顶片的其它膜不向外凸出。

公开(公告)号：US06570707B1

公开(公告)日：2003-05-27

申请号：US09708879

申请日：2000-11-08

申请人： Yukio Murakami ,  Shunsuke Hirano

发明人： Yukio Murakami ,  Shunsuke Hirano

IPC分类号： G02B530

CPC分类号： G06F3/045 ,  G06F3/0414

摘要： A touch panel is constructed of a top sheet member having a resistive membrane on its inner surface and a base sheet member having a resistive membrane on its inner surface, the top and base sheet members facing each other with dot spacers being located in between. The top sheet member is formed by laminating a bulge-resistant film, a polarizing plate, a quarter wavelength plate, and a light isotropic film in this order from above. The base sheet member is constructed of a glass sheet and a reinforcement film whose thermal linear expansion coefficient is almost the same as the thermal linear expansion coefficient of the polarizing plate or the quarter wavelength plate included in the top sheet member, the reinforcement film being adhered to the lower surface of the glass sheet.

摘要翻译： 触摸面板由在其内表面上具有电阻膜的顶片构件和在其内表面上具有电阻膜的基片构件构成，顶片和基片构件彼此面对，点间隔物位于其间。 通过从上方按顺序层叠防胀薄膜，偏振板，四分之一波长板和光各向同性膜而形成顶片部件。 基片构件由玻璃板和加热膜构成，其热线膨胀系数与包括在顶片构件中的偏振板或四分之一波长板的热线膨胀系数几乎相同，增强膜粘附 到玻璃板的下表面。

公开(公告)号：US07826811B2

公开(公告)日：2010-11-02

申请号：US11594979

申请日：2006-11-09

申请人： Hiroyuki Yoshikawa ,  Shunsuke Hirano

发明人： Hiroyuki Yoshikawa ,  Shunsuke Hirano

IPC分类号： H04B1/16

CPC分类号： H04L27/2092 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/095 ,  H03C5/00

摘要： A two-point modulation type phase apparatus and a wireless communication apparatus capable of achieving a reduction in circuit scale and low power consumption while maintaining modulation precision. It is possible to provide a D/A converter (150) that converts the inputted digital baseband signal to an analog signal, an adder (110) that adds an output signal of a D/A converter (150) and an output of a loop filter (135) to output to a control voltage terminal of the voltage controlled oscillator (105), and a peak control section (140) provided at a front stage of the D/A converter (150) that carries out smoothing of peak portions appearing at the inputted digital baseband signal, at a two-point modulation type phase modulation apparatus (100) that modulates a-carrier frequency signal using an inputted digital baseband signal by setting a frequency dividing ratio of a frequency divider (115) of a PLL circuit based on an inputted digital baseband modulation signal, and adding a voltage corresponding to a signal that is an inputted digital baseband signal analog-converted for supply to a control voltage terminal of a voltage controlled oscillator (105).

摘要翻译： 一种两点调制型相位装置和无线通信装置，其能够在保持调制精度的同时实现电路规模的降低和低功耗。 可以提供将输入的数字基带信号转换为模拟信号的D / A转换器（150），将D / A转换器（150）的输出信号和循环的输出相加的加法器（110） 滤波器（135）输出到压控振荡器（105）的控制电压端，以及峰值控制部（140），设置在D / A转换器（150）的前级，其执行出现峰值部分的平滑化 在输入的数字基带信号的两点调制型相位调制装置（100）中，通过设定PLL电路的分频器（115）的分频比，使用输入的数字基带信号来调制a载波频率信号 基于输入的数字基带调制信号，并将与作为模拟转换的输入数字基带信号的信号相对应的电压相加，供给压控振荡器（105）的控制电压端。

公开(公告)号：US20100073095A1

公开(公告)日：2010-03-25

申请号：US12566347

申请日：2009-09-24

申请人： Shunsuke Hirano

发明人： Shunsuke Hirano

IPC分类号： H03L7/085

CPC分类号： H03L7/18 ,  H03L7/085 ,  H03L7/185 ,  H03L2207/12

摘要： A frequency synthesizer (100) can selectively set an output band of VCO, and consumes less power. The frequency synthesizer (100) has a frequency converting circuit (110) that has a mixer (111) and a frequency divider (112) connected with each other in parallel. The frequency synthesizer (100) uses the frequency divider (112) upon frequency band selection in VCO (101) and uses the mixer (111) upon transmission.

摘要翻译： 频率合成器（100）可以选择性地设置VCO的输出频带，并且消耗更少的功率。 频率合成器（100）具有频率转换电路（110），其具有并联连接的混频器（111）和分频器（112）。 频率合成器（100）在VCO（101）中进行频带选择时使用分频器（112），并且在发送时使用混频器（111）。

公开(公告)号：US07236063B2

公开(公告)日：2007-06-26

申请号：US10539426

申请日：2004-07-22

申请人： Taketoshi Ochi ,  Shunsuke Hirano

发明人： Taketoshi Ochi ,  Shunsuke Hirano

IPC分类号： H03B5/00

CPC分类号： H03C3/0991 ,  H03C3/0916 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0958 ,  H03C3/0966 ,  H03L7/099 ,  H03L7/197 ,  H03L2207/06

摘要： A problem of the present invention is to provide a wide band modulation PLL having good modulation accuracy at low cost. With respect to a PLL having a VCO (21), a frequency divider (22), a phase comparator (23), a charge pump (24) and a loop filter (25), the VCO (21) and a frequency dividing ratio of the frequency divider (22) are controlled to perform modulation. The VCO (21) has two control terminals for PLL and modulation, and a control signal generation part (28) generates a control voltage Vtm of the VCO (21) based on phase modulation data and an input voltage Vtl to the control terminal for PLL. At the time of adjusting a modulation factor, the control voltage Vtm to the control terminal for modulation of the VCO (21) is controlled and also the input voltage Vtl is measured and a modulation sensitivity of a frequency of the VCO (21) to Vtm is calculated and a modulation factor of the phase modulation data is adjusted based on the modulation sensitivity obtained.

摘要翻译： 本发明的一个问题是以低成本提供具有良好调制精度的宽带调制PLL。 对于具有VCO（21），分频器（22），相位比较器（23），电荷泵（24）和环路滤波器（25）的PLL，VCO（21）和分频比 控制分频器（22）进行调制。 VCO（21）具有用于PLL和调制的两个控制端子，并且控制信号生成部件（28）基于相位调制数据和输入端产生VCO（21）的控制电压V tm 电压V L1到PLL的控制端子。 在调整调制因子时，控制用于调制VCO（21）的控制端子的控制电压V SUB，并且输入电压V SUB1是 并且计算VCO（21）的频率到V tm的调制灵敏度，并且基于所获得的调制灵敏度来调整相位调制数据的调制系数。

公开(公告)号：US20060115036A1

公开(公告)日：2006-06-01

申请号：US11333245

申请日：2006-01-18

申请人： Hisashi Adachi ,  Toshifumi Nakatani ,  Hiroaki Kosugi ,  Masakatsu Maeda ,  Shunsuke Hirano

发明人： Hisashi Adachi ,  Toshifumi Nakatani ,  Hiroaki Kosugi ,  Masakatsu Maeda ,  Shunsuke Hirano

IPC分类号： H03D3/24

CPC分类号： H03L7/1976

摘要： A fraction part control circuit of a frequency synthesizer apparatus including a PLL circuit is of a plural-n-th-order delta-sigma modulator circuit for controlling a fraction part of a number of frequency division to a variable frequency divider of the PLL circuit. An adder adds data of the fraction part to an output data from a multiplier and outputs the resultant data to a quantizer through a second-order integrator. The quantizer quantizes input data with a quantization step and outputs the quantized data to the multiplier through a feedback circuit. The quantized data is used as data of the controlled fraction part. The multiplier multiplies data from the feedback circuit by the quantization step and outputs the resultant data to the adder. The fraction part control circuit periodically changes the data of the fraction part, thereby setting a frequency of an output signal from a VCO according to an average value of the period.

摘要翻译： 包括PLL电路的频率合成器装置的分数部分控制电路是用于控制与PLL电路的可变分频器分频的分数部分的多n-Δ级Δ-Σ调制器电路。 加法器将分数部分的数据与来自乘法器的输出数据相加，并将结果数据通过二阶积分器输出到量化器。 量化器用量化步长量化输入数据，并通过反馈电路将量化的数据输出到乘法器。 量化数据用作受控分数部分的数据。 乘法器将来自反馈电路的数据乘以量化步长，并将结果数据输出到加法器。 分数部分控制电路周期性地改变分数部分的数据，从而根据周期的平均值设置来自VCO的输出信号的频率。

公开(公告)号：US20050271159A1

公开(公告)日：2005-12-08

申请号：US11080680

申请日：2005-03-16

申请人： Hiroyuki Yoshikawa ,  Hisashi Adachi ,  Shunsuke Hirano

发明人： Hiroyuki Yoshikawa ,  Hisashi Adachi ,  Shunsuke Hirano

IPC分类号： H03C3/00 ,  H03C3/09 ,  H04L27/04 ,  H04L27/12 ,  H04L27/20

CPC分类号： H03C3/0933 ,  H03C3/0925 ,  H04L27/12 ,  H04L27/2003

摘要： A frequency modulation apparatus 100 has a synthesizer 101, a differentiator 102 that differentiates phase modulation data and generates differential phase modulation data, an adder 103 that adds together that differential phase modulation data and carrier frequency data fractional part K and generates addition fractional part K1, an input data operation section 104 that receives addition fractional part K1 and carrier frequency data integer part M, generates integer part input data M1 and fractional part input data K2, and provides fractional part input data K2 to synthesizer 101, and an integer part data delay section 105 that delays integer part input data M1 before providing it to synthesizer 101. Input data operation section 104 makes M1=M−1 and K2=K1+1 when K1

摘要翻译： 频率调制装置100具有合成器101，微分器102，其对相位调制数据进行微分并产生差分相位调制数据;加法器103，将差分相位调制数据和载波频率数据小数部分K相加，生成加法分数部分K 1 ，接收加法分数部分K 1和载波频率数据整数部分M的输入数据操作部分104产生整数部分输入数据M 1和小数部分输入数据K 2，并向合成器101提供分数部分输入数据K 2，以及 整数部分数据延迟部分105，其在将整数部分输入数据M 1提供给合成器101之前将其延迟。 当K 1 <0时，输入数据运算部104使M 1 = M-1，K 2 = K 1 +1，当0 <= K 1 <1时，M 1 = M，K 2 = K 1，使M 1 = 1 + = 1，K 2 = K 1 -1。

公开(公告)号：US06728526B2

公开(公告)日：2004-04-27

申请号：US09794185

申请日：2001-02-26

申请人： Ryoichi Yamada ,  Shunsuke Hirano ,  Yasunori Miyahara ,  Hisashi Adachi ,  Hisashi Takahashi ,  Hiroki Kojima

发明人： Ryoichi Yamada ,  Shunsuke Hirano ,  Yasunori Miyahara ,  Hisashi Adachi ,  Hisashi Takahashi ,  Hiroki Kojima

IPC分类号： H04B106

CPC分类号： H03L7/1976

摘要： A frequency synthesizer device comprising a PLL circuit (9) and a frequency-division ratio control circuit (5). The PLL circuit (9) includes a phase comparator (1), a low-pass filter (2), a voltage-controlled oscillator (3), and a variable frequency divider (4). The frequency-division ratio control circuit (5) controls the variable frequency divider (4) such that a frequency division ratio of the variable frequency divider (4) is changed in time and a time average value of the frequency division ratio contains a value below a decimal point. Two different signals of an output signal fdiv of the variable frequency divider (4) and an output fdiv2 obtained via a delay element (10) are used as clocks of an accumulator portion (81) in the frequency-division ratio control circuit (5). The variation in the substrate potential and the variation in the power supply voltage generated by the operation of the frequency-division ratio control circuit (5) can be reduced, and the degradation of C/N of the frequency synthesizer can be suppressed.

摘要翻译： 一种频率合成器装置，包括PLL电路（9）和分频比控制电路（5）。 PLL电路（9）包括相位比较器（1），低通滤波器（2），压控振荡器（3）和可变分频器（4）。 分频比控制电路（5）控制可变分频器（4），使得可变分频器（4）的分频比在时间上变化，并且分频比的时间平均值包含低于 小数点。 使用分频比控制电路（5）中的可变分频器（4）的输出信号fdiv和通过延迟元件（10）获得的输出fdiv2的两个不同信号作为累加器部分（81）的时钟， 。 可以减小由分频比控制电路（5）的操作产生的基板电位的变化和电源电压的变化，并且可以抑制频率合成器的C / N的劣化。

公开(公告)号：US20130148769A1

公开(公告)日：2013-06-13

申请号：US13816156

申请日：2012-02-06

申请人： Shunsuke Hirano

发明人： Shunsuke Hirano

IPC分类号： H04L7/033

CPC分类号： H04L7/033 ,  H03L7/0805 ,  H03L7/18

摘要： A wireless apparatus includes a clock generation PLL circuit of a digital baseband section. A variable output regulator receives as an input a VCO control voltage for controlling an oscillation frequency of a VCO in the PLL circuit, varies an output voltage in accordance with the VCO control voltage, and supplies, as a supply voltage, the output voltage to a power terminal of a high frequency circuit, such as an amplifier. The VCO control voltage changes in accordance with temperature or process variations, and the supply voltage of the high frequency circuit is controlled in accordance with the VCO control voltage. For this reason, performance deterioration ascribable to the temperature or process variations can be compensated for.

摘要翻译： 无线装置包括数字基带部分的时钟产生PLL电路。 可变输出调节器接收用于控制PLL电路中的VCO的振荡频率的VCO控制电压作为输入，根据VCO控制电压改变输出电压，并将输出电压作为电源电压提供给 高频电路的电源端子，如放大器。 VCO控制电压根据温度或工艺变化而变化，高频电路的电源电压根据VCO控制电压进行控制。 为此，可以补偿归因于温度或工艺变化的性能劣化。