公开(公告)号：US5406875A

公开(公告)日：1995-04-18

申请号：US20307

申请日：1993-02-19

申请人： Yutaka Tamai ,  Yoshiaki Shimoda ,  Kazuhiro Tsukamoto

发明人： Yutaka Tamai ,  Yoshiaki Shimoda ,  Kazuhiro Tsukamoto

IPC分类号： G10H1/34 ,  G10C3/12

CPC分类号： G10H1/344

摘要： A keyboard apparatus for an electronic musical instrument has a metallic keyboard chassis and a balance rail provided on the keyboard chassis. A plurality of pins are provided on the balance rail. The pins and the balance +*rail constitute fulcrums for swingably supporting white keys and black keys. The fulcrums for the black keys are disposed on the same line with, or in front of, the fulcrums for the white keys. Hammers are provided in a rear of the keys so as to be swingable by swinging of each of the respective keys. The hammers are disposed on the same axis of rotation, and a position for the black keys to operate to swing the respective hammers is located in front of a position for the white keys to operate to swing the respective hammers such that an angle of rotation of the respective hammers becomes substantially equal to each other. A stopper member for restricting the swinging movement of the keys or the hammers are provided in a rear upper portion of the keys. The metallic key board chassis is divided into a front chassis portion and a rear chassis portion, and the two are connected by metallic reinforcing beams.

摘要翻译： 用于电子乐器的键盘装置具有金属键盘机箱和设置在键盘机箱上的平衡导轨。 在平衡轨上设有多个销。 针脚和平衡+ *导轨构成了可摆动支撑白键和黑键的支点。 用于黑键的支点设置在与白键的支点相同的线上或在其前方。 锤子设置在键的后部，以便通过各个键的摆动摆动。 锤子设置在相同的旋转轴线上，并且用于使黑色键操作以摆动相应锤的位置位于用于使白键移动的位置的前方，以使各个锤子摆动，使得旋转角度 相应的锤子基本上彼此相等。 用于限制键或锤的摆动的止动构件设置在键的后部上部。 金属键盘底盘分为前机箱部分和后机架部分，两者通过金属加强梁连接。

公开(公告)号：US5542332A

公开(公告)日：1996-08-06

申请号：US353989

申请日：1994-12-06

申请人： Yutaka Tamai ,  Yoshiaki Shimoda ,  Kazuhiro Tsukamoto

发明人： Yutaka Tamai ,  Yoshiaki Shimoda ,  Kazuhiro Tsukamoto

IPC分类号： G10H1/34 ,  G10C3/12

CPC分类号： G10H1/344

摘要： A keyboard apparatus for an electronic musical instrument has a metallic keyboard chassis and a balance rail provided on the keyboard chassis. A plurality of pins are provided on the balance rail. The pins and the balance rail constitute fulcrums for swingably supporting white keys and black keys. A hammer is provided in a rear side of each of the white and the black keys so as to be swingable by swinging of each of the respective keys by a second fulcrum comprising oval cross sectional shafts extending outwardly from the side surface of one of the hammer and a bearing member, the side surface extending perpendicular to a direction of swing movement of the hammer and a pair of bearing recesses for pivotally receiving the shaft, the bearing recesses being formed in the other of the hammer and the bearing member. Each of the bearing recesses has a guide slot for guiding each of the shafts from outside into the bearing recess for assembling. A split groove is provided in the other of the hammer and the bearing member for receiving the one of the hammer and the bearing member. First abutment surfaces are provided so as to project in an axial direction of the shafts from the side surface of the one of the hammer and the bearing member around the shafts, the first abutment surfaces being in sliding contract with the slit groove. Second abutment surfaces are provided by reducing the width between the side surfaces and lateral vibration preventing surfaces are provided inside the split groove in close proximity to the second abutment surfaces.

摘要翻译： 用于电子乐器的键盘装置具有金属键盘机箱和设置在键盘机箱上的平衡导轨。 在平衡轨上设有多个销。 销和平衡轨构成支点，用于可摆动地支撑白键和黑键。 在每个白色和黑色键的后侧设置有锤子，以便通过第二支点摆动各个键的摆动，所述第二支点包括椭圆形横截面轴，从所述锤中的一个的侧面向外延伸 以及轴承构件，所述侧面垂直于所述锤的摆动运动的方向延伸，所述一对轴承凹部用于枢转地接收所述轴，所述轴承凹部形成在所述锤和所述轴承构件中的另一个中。 每个轴承凹槽具有用于将每个轴从外部引导到用于组装的轴承凹部中的引导槽。 在另一个锤和轴承构件中设置有分接槽，用于接收锤和轴承构件中的一个。 第一抵接面设置成从轴的轴承部件的侧面和轴的轴向突出，第一抵接面与狭缝槽滑动接合。 通过减小侧表面之间的宽度来设置第二邻接表面，并且横向防振表面设置在裂缝槽内部，紧邻第二邻接表面。

公开(公告)号：US06888245B2

公开(公告)日：2005-05-03

申请号：US10222814

申请日：2002-08-19

申请人： Kazuhiro Tsukamoto

发明人： Kazuhiro Tsukamoto

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L29/40

CPC分类号： H01L21/76889 ,  H01L21/28518 ,  H01L23/485 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a conductive layer formed on a silicon semiconductor substrate, cobalt silicide films formed in a surface layer of the conductive layer, an interlayer insulating film which covers the silicon semiconductor substrate thereabove, and a barrier metal film and a tungsten film which fill in a contact hole formed in the interlayer insulating film and is electrically connected to the cobalt silicide film. The positions of lower surfaces of the cobalt silicide films at the bottom of the contact hole are set lower than the position of a lower surface of the cobalt silicide film provided outside the contact hole. A cobalt silicide film having a necessary thickness can be ensured at the bottom of the contact hole. Further, a contact resistance can be reduced and a junction leak can be suppressed.

摘要翻译： 半导体器件包括形成在硅半导体衬底上的导电层，形成在导电层的表面层中的钴硅化物膜，覆盖其上面的硅半导体衬底的层间绝缘膜，以及阻挡金属膜和填充 在形成在层间绝缘膜中并与硅化钴膜电连接的接触孔中。 接触孔底部的硅化钴膜的下表面的位置被设定为低于设置在接触孔外侧的硅化钴膜的下表面的位置。 可以在接触孔的底部确保具有必要厚度的硅化钴膜。 此外，可以降低接触电阻并且可以抑制结泄漏。

公开(公告)号：US4934826A

公开(公告)日：1990-06-19

申请号：US211548

申请日：1988-06-24

申请人： Hideshi Miyatake ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Kazuhiro Tsukamoto

发明人： Hideshi Miyatake ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Kazuhiro Tsukamoto

IPC分类号： G11C11/406 ,  G11C11/408 ,  G11C11/409

CPC分类号： G11C11/409 ,  G11C11/406 ,  G11C11/408

摘要： A word line driving signal generating circuit and a sense amplifier activating signal generating circuit are provided for every partitioned memory cell array. When the levels of an external RAS signal and an external CAS signal have a predetermined relation and an external RNC signal remains at a predetermined potential or more, a refresh operation is started. A refresh address is generated from a refresh address counter in a sense restore control circuit. All of the memory cell arrays are simultaneously refreshed in response to the address. On this occasion, an operation for selecting a column by a column decoder provided in each of the memory cell arrays is inhibited. In the case in which an input of the external RNC signal is not prepared, when the levels of the external RAS signal and the external CAS signal have a predetermined relation and this state is held in a predetermined time period or more, the same refresh operation as described above is started.

摘要翻译： 为每个分区存储单元阵列提供字线驱动信号发生电路和读出放大器激活信号产生电路。 当外部RAS信号和外部CAS信号的电平具有预定关系并且外部RNC信号保持在预定电位或更大时，开始刷新操作。 从感测恢复控制电路中的刷新地址计数器产生刷新地址。 响应于地址，所有的存储单元阵列被同时刷新。 在这种情况下，禁止通过设置在每个存储单元阵列中的列解码器来选择列的操作。 在没有准备外部RNC信号的输入的情况下，当外部RAS信号和外部CAS信号的电平具有预定关系并且该状态保持在预定时间段或更长时间时，相同的刷新操作 如上所述开始。

公开(公告)号：US08384160B2

公开(公告)日：2013-02-26

申请号：US12627060

申请日：2009-11-30

申请人： Kazuhiro Onishi ,  Kazuhiro Tsukamoto

发明人： Kazuhiro Onishi ,  Kazuhiro Tsukamoto

IPC分类号： H01L21/70

CPC分类号： H01L21/823462 ,  G11C11/412 ,  H01L21/82345 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used, the reduction of the drive current of a MIS transistor having a greater absolute value of threshold voltage. The threshold voltage of a second nMIS transistor is greater than the threshold voltage of a first nMIS transistor and the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a second nMIS high-k film included in the second nMIS transistor is lower than the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a first nMIS high-k film included in the first nMIS transistor.

公开(公告)号：US07777280B2

公开(公告)日：2010-08-17

申请号：US12263130

申请日：2008-10-31

申请人： Kazuhiro Tsukamoto

发明人： Kazuhiro Tsukamoto

IPC分类号： H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  H01L29/665

摘要： There have been provided a semiconductor device capable of preventing defects associated with etching, such as an increase in leak current, deterioration in film-coating properties and deterioration in transistor properties, and a method for manufacturing the semiconductor device. A CMOS transistor includes, on the same semiconductor substrate, an NMOS transistor having a gate electrode and a PMOS transistor having a gate electrode, wherein the former gate electrode includes a gate insulating film, a polycrystal silicon layer, a metal layer and another polycrystal silicon layer, and the latter gate electrode includes a gate insulating film, a metal layer and a polycrystal silicon layer.

摘要翻译： 已经提供了能够防止与蚀刻相关的缺陷的半导体器件，例如泄漏电流的增加，膜包覆性能的劣化和晶体管特性的劣化，以及半导体器件的制造方法。 CMOS晶体管在相同的半导体衬底上包括具有栅电极和PMOS晶体管的NMOS晶体管，其具有栅电极，其中前栅电极包括栅极绝缘膜，多晶硅层，金属层和另一多晶硅 并且后一栅电极包括栅极绝缘膜，金属层和多晶硅层。

公开(公告)号：US4843596A

公开(公告)日：1989-06-27

申请号：US124554

申请日：1987-11-24

申请人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

发明人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

IPC分类号： G11C11/401 ,  G11C7/22 ,  G11C8/18

CPC分类号： G11C8/18 ,  G11C7/22

摘要： A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.

摘要翻译： 一种新颖的半导体存储器件包括响应于地址变化的检测而产生短宽度脉冲的地址检测电路。 列解码器激活信号发生器检测短宽度脉冲的开始，并且响应于产生列解码器激活信号。 第二检测电路检测短宽度脉冲的结论，并产生触发前置放大器激活信号的第二脉冲，其激活前置放大器并锁存输入/输出线上存在的数据。 复位信号发生器产生复位信号以停用列解码器激活信号并延迟前置放大器激活信号。 当输出第一个脉冲时，前置放大器激活信号发生器和复位信号发生器被复位。

公开(公告)号：US4823322A

公开(公告)日：1989-04-18

申请号：US102683

申请日：1987-09-30

申请人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

发明人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/413 ,  G11C7/00

CPC分类号： G11C11/4076

摘要： A dynamic random access memory device having an input/output load connected between a pair of input/output lines and a control circuit used to generate an internal /RAS signal having a reset transition delayed with respect to the same transition of the external /RAS signal. The internal /RAS signal controls at least a word signal applied to a transistor of a selected memory cell and an enable signal applied to an enable transistor, whereby the time the transistor of the memory cell and the enable transistor become non-conductive is delayed with respect to the time at which a transfer transistor connected between each pair of bit lines and the input/output lines becomes non-conductive.

摘要翻译： 具有连接在一对输入/输出线之间的输入/输出负载和用于产生内部/ RAS信号的动态随机存取存储器件，该内部/ RAS信号具有相对于外部/ RAS信号的相同转变延迟的复位转变 。 内部/ RAS信号至少控制施加到所选择的存储单元的晶体管的字信号和施加到使能晶体管的使能信号，从而使存储器单元和使能晶体管变为不导通的时间被延迟 相对于连接在每对位线和输入/输出线之间的传输晶体管的时间变得不导通。

公开(公告)号：US20100164007A1

公开(公告)日：2010-07-01

申请号：US12627060

申请日：2009-11-30

申请人： Kazuhiro ONISHI ,  Kazuhiro Tsukamoto

发明人： Kazuhiro ONISHI ,  Kazuhiro Tsukamoto

IPC分类号： H01L27/088 ,  H01L27/11 ,  H01L21/8234

CPC分类号： H01L21/823462 ,  G11C11/412 ,  H01L21/82345 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used, the reduction of the drive current of a MIS transistor having a greater absolute value of threshold voltage.The threshold voltage of a second nMIS transistor is greater than the threshold voltage of a first nMIS transistor and the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a second nMIS high-k film included in the second nMIS transistor is lower than the sum of the concentration of lanthanum atom and the concentration of magnesium atom in a first nMIS high-k film included in the first nMIS transistor.

摘要翻译： 为了提供一种半导体器件及其制造方法，当使用具有不同的阈值电压绝对值的多个MIS晶体管时，能够抑制阈值电压绝对值较大的MIS晶体管的驱动电流的降低 。 第二nMIS晶体管的阈值电压大于第一nMIS晶体管的阈值电压，并且包含在第二nMIS晶体管中的第二nMIS高k膜中的镧原子浓度与镁原子浓度之和较低 比第一nMIS晶体管中包含的第一nMIS高k膜中的镧原子浓度和镁原子浓度的总和。

公开(公告)号：US06483140B1

公开(公告)日：2002-11-19

申请号：US09481387

申请日：2000-01-12

申请人： Takeru Matsuoka ,  Kazuhiro Tsukamoto

发明人： Takeru Matsuoka ,  Kazuhiro Tsukamoto

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10873 ,  H01L27/10888

摘要： A lower insulating film is formed so as to cover source/drain regions electrically connected to capacitors. Bit lines and upper insulating layers are formed on the lower insulating film. SCs opening to the lower insulating film are formed by an anisotropic etching process on process conditions for etching the upper insulating films at a high upper insulating film/lower insulating film selectivity. An insulating film of a quality equal to that of the lower insulating film is deposited so as to fill up the SCs and to cover the upper insulating film. The SCs is extended so as to open to the source/drain regions by an anisotropic etching process on process conditions for etching the lower insulating film at a high lower insulating film/silicon film selectivity.

摘要翻译： 形成下绝缘膜以覆盖与电容器电连接的源极/漏极区域。 位线和上绝缘层形成在下绝缘膜上。 通过各向异性蚀刻工艺，以高上绝缘膜/下绝缘膜选择性蚀刻上绝缘膜的工艺条件形成通向下绝缘膜的SC。 沉积质量等于下绝缘膜的绝缘膜，以填充SC并覆盖上绝缘膜。 通过各向异性蚀刻工艺对SCs进行扩展，以在较低的绝缘膜/硅膜选择性下蚀刻下绝缘膜的工艺条件下对源/漏区开放。