公开(公告)号：US20090003103A1

公开(公告)日：2009-01-01

申请号：US12142278

申请日：2008-06-19

申请人： Yuui SHIMIZU ,  Shigeo Ohshima ,  Mie Matsuo

发明人： Yuui SHIMIZU ,  Shigeo Ohshima ,  Mie Matsuo

IPC分类号： G11C5/14 ,  G11C8/00

CPC分类号： G11C5/145 ,  G11C5/04 ,  G11C5/066 ,  G11C5/143 ,  G11C16/30 ,  G11C29/12005 ,  G11C29/48 ,  G11C29/56 ,  G11C2029/5602 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/01019 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.

摘要翻译： 提供半导体器件，半导体存储器测试器和多芯片封装。 半导体器件包括多个非易失性半导体存储器; 升压电路，其产生用于操作所述多个非易失性半导体存储器的升压电压; 以及升压电路控制器，其基于所述多个非易失性半导体存储器的操作顺序来控制所述升压电路的操作以产生所述升压电压。

公开(公告)号：US20120025865A1

公开(公告)日：2012-02-02

申请号：US13191825

申请日：2011-07-27

申请人： Yuui SHIMIZU

发明人： Yuui SHIMIZU

IPC分类号： H03K19/0175 ,  H03K19/00

CPC分类号： H03K19/018521 ,  H03K19/018585

摘要： According to one embodiment, an input circuit includes an input buffer, a control unit, a holding unit, a feedback unit. The input buffer receives a signal input from an outside. The input buffer includes a plurality of CMOS inverters connected in parallel. The plurality of CMOS inverters includes a plurality of PMOS transistors and a plurality of NMOS transistors. The control unit selects one or more PMOS transistors from the plurality of PMOS transistors so as to enter an operable state. The control unit selects one or more NMOS transistors from the plurality of NMOS transistors so as to enter an operable state. The holding unit holds a level of a signal transferred from the input buffer in synchronization with a clock signal. The holding unit outputs the held signal level. The feedback unit feeds the level of the signal output from the holding unit back to the control unit.

摘要翻译： 根据一个实施例，输入电路包括输入缓冲器，控制单元，保持单元，反馈单元。 输入缓冲器接收从外部输入的信号。 输入缓冲器包括并联连接的多个CMOS反相器。 多个CMOS反相器包括多个PMOS晶体管和多个NMOS晶体管。 控制单元从多个PMOS晶体管中选择一个或多个PMOS晶体管，以进入可操作状态。 控制单元从多个NMOS晶体管中选择一个或多个NMOS晶体管，以进入可操作状态。 保持单元保持与时钟信号同步地从输入缓冲器传送的信号的电平。 保持单元输出保持的信号电平。 反馈单元将从保持单元输出的信号的电平返回到控制单元。

公开(公告)号：US20080186759A1

公开(公告)日：2008-08-07

申请号：US12026077

申请日：2008-02-05

申请人： Yuui SHIMIZU ,  Tatsuya Kishi

发明人： Yuui SHIMIZU ,  Tatsuya Kishi

IPC分类号： G11C11/00 ,  G11C11/14

CPC分类号： G11C11/16

摘要： A magnetic random access memory includes a first interconnection extending to a first direction, a second interconnection extending to a second direction perpendicular to the first direction, a magnetoresistive effect element formed between the first and second interconnections, having one terminal connected to the first interconnection, includes a fixed layer, a recording layer and a nonmagnetic layer, a film thickness of the fixed layer being larger than that of the recording layer, and a width of the fixed layer being larger than that of the recording layer, and configured to reverse a magnetization direction in the recording layer by supplying a first electric current between the fixed layer and the recording layer, and a diode having one terminal connected to the other terminal of the magnetoresistive effect element, and the other terminal connected to the second interconnection, and configured to supply the first electric current in only one direction.

摘要翻译： 磁性随机存取存储器包括延伸到第一方向的第一互连，延伸到垂直于第一方向的第二方向的第二互连，形成在第一和第二互连之间的磁阻效应元件，具有连接到第一互连的一个端子， 包括固定层，记录层和非磁性层，固定层的膜厚度大于记录层的厚度，固定层的宽度大于记录层的厚度， 通过在固定层和记录层之间提供第一电流而形成记录层中的磁化方向，以及二极管，其一端连接到磁阻效应元件的另一端，另一端连接到第二互连， 以仅在一个方向上提供第一电流。

公开(公告)号：US20130027108A1

公开(公告)日：2013-01-31

申请号：US13524391

申请日：2012-06-15

申请人： Yuui SHIMIZU ,  Masaru KOYANAGI

发明人： Yuui SHIMIZU ,  Masaru KOYANAGI

IPC分类号： H03L5/00

摘要： According to one embodiment, a level shift circuit includes a plurality of level shift units which are connected to each other and in which the delay time of the rising edge of an output voltage is different from the delay time of the falling edge of the output voltage. The delay time of the rising edge of the output voltage from the previous level shift unit is compensated by the delay time of the falling edge of the output voltage from the next level shift unit, and the delay time of the falling edge of the output voltage from the previous level shift unit is compensated by the delay time of the rising edge of the output voltage from the next level shift unit.

摘要翻译： 根据一个实施例，电平移位电路包括彼此连接的多个电平移位单元，其中输出电压的上升沿的延迟时间与输出电压的下降沿的延迟时间不同 。 来自先前电平移位单元的输出电压的上升沿的延迟时间由下一个电平移位单元的输出电压的下降沿的延迟时间补偿，并且输出电压的下降沿的延迟时间 来自先前电平移位单元的输出电压的上升沿的延迟时间由下一个电平移位单元补偿。

公开(公告)号：US20080253173A1

公开(公告)日：2008-10-16

申请号：US11863997

申请日：2007-09-28

申请人： Yuui SHIMIZU ,  Tsuneo INABA

发明人： Yuui SHIMIZU ,  Tsuneo INABA

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C29/52 ,  G11C11/16 ,  G11C2029/0409

摘要： A magnetic random access memory according to an example of the invention comprises a first reference bit line shared by first reference cells, a second reference bit line shared by second reference cells, a first driver-sinker to feed a first writing current, a second driver-sinker to feed a second writing current, and a control circuit which checks data stored in the first and second reference cells line by line, and executes writing simultaneously to all of the first and second reference cells by a uniaxial writing when the data is broken.

摘要翻译： 根据本发明的示例的磁随机存取存储器包括由第一参考单元共享的第一参考位线，由第二参考单元共享的第二参考位线，用于馈送第一写入电流的第一驱动器沉降器，第二驱动器 用于馈送第二写入电流的控制电路，以及一行一行地检查存储在第一和第二参考单元中的数据的控制电路，并且当数据被破坏时通过单轴写入同时执行对所有第一和第二参考单元的写入 。

公开(公告)号：US20130250693A1

公开(公告)日：2013-09-26

申请号：US13602626

申请日：2012-09-04

申请人： Yuui SHIMIZU

发明人： Yuui SHIMIZU

IPC分类号： G11C16/32

CPC分类号： G11C16/32 ,  G11C7/1066 ,  G11C16/26 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

摘要： According to one embodiment, a memory system includes a first semiconductor memory and a controller. The first semiconductor memory receives a first clock, and outputs, in accordance with the first clock, a second clock and a data signal in synchronization with the second clock. The controller includes a detection circuit which detects a shift of a duty ratio of the second clock which is output from the first semiconductor memory. The controller also includes an adjustment circuit which adjusts a duty ratio of the first clock based on the shift detected by the detection circuit.

摘要翻译： 根据一个实施例，存储器系统包括第一半导体存储器和控制器。 第一半导体存储器接收第一时钟，并且根据第一时钟输出与第二时钟同步的第二时钟和数据信号。 控制器包括检测电路，其检测从第一半导体存储器输出的第二时钟的占空比的偏移。 控制器还包括调整电路，该调整电路根据由检测电路检测到的移位来调节第一时钟的占空比。

公开(公告)号：US20090122611A1

公开(公告)日：2009-05-14

申请号：US12266734

申请日：2008-11-07

申请人： Yuui SHIMIZU ,  Toshiaki EDAHIRO

发明人： Yuui SHIMIZU ,  Toshiaki EDAHIRO

IPC分类号： G11C16/04 ,  G11C8/00 ,  G11C11/34 ,  G11C16/06

CPC分类号： G11C8/08 ,  G11C8/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621

摘要： This disclosure concerns a memory including cell blocks, wherein in a first write sequence for writing data to a first cell block, drivers write the data only to memory cells arranged in a form of a checkered flag among the memory cells included in the first cell block, in a second write sequence for writing the data from the first cell block to a second cell block, the drivers write the data to all memory cells connected to a word line selected in the second cell block, and when the data is read from the first cell block or at a time of data verification when data is written to the first cell block, the word line drivers simultaneously apply a read voltage to two adjacent word lines, and the sense amplifiers detects the data in the memory cells connected to the two word lines.

摘要翻译： 本公开涉及包括单元块的存储器，其中在用于将数据写入第一单元块的第一写入序列中，驱动器将数据仅写入到以包括在第一单元块中的存储单元中的格状标志形式布置的存储单元 在用于将数据从第一单元块写入第二单元块的第二写入序列中，驱动器将数据写入连接到在第二单元块中选择的字线的所有存储器单元，并且当数据从 第一单元块，或者当数据被写入第一单元块时的数据验证时，字线驱动器同时向两个相邻的字线施加读取电压，并且读出放大器检测连接到两个单元的存储单元中的数据 字线。

公开(公告)号：US20110305086A1

公开(公告)日：2011-12-15

申请号：US13159696

申请日：2011-06-14

申请人： Tomofumi FUJIMURA ,  Yuui SHIMIZU

发明人： Tomofumi FUJIMURA ,  Yuui SHIMIZU

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G11C29/808

摘要： A memory includes stacking chips. The chip includes a pad commonly connected to the chips and receiving an enable signal that enables access to each chip. The chip includes a chip address memory that can store a chip address. The chip includes a determining part comparing a select address to the chip address for determining whether they match each other. The chip includes a control-signal setting part setting the control signal inputted to the chip itself to be valid or invalid depending on a determination made by the determining part. The chip includes a chip-address setting part determining whether the chip address is stored in the chip address memory depending on number of fail bits. The device includes a memory controller allocating respectively different ones of the chip addresses to the chips based on the number of fail bits.

摘要翻译： 存储器包括堆叠芯片。 该芯片包括通常连接到芯片的接收器，并且接收能够接入每个芯片的使能信号。 该芯片包括可存储芯片地址的芯片地址存储器。 芯片包括将选择地址与芯片地址进行比较以确定它们是否彼此匹配的确定部分。 该芯片包括控制信号设定部，其根据由判定部作出的判定，将输入到芯片本身的控制信号设定为有效或无效。 芯片包括芯片地址设定部，根据故障位的数量来判定芯片地址是否存储在芯片地址存储器中。 该装置包括一个存储器控制器，该存储器控制器基于故障位数来分别分配不同芯片地址到芯片。

公开(公告)号：US20110267864A1

公开(公告)日：2011-11-03

申请号：US13052198

申请日：2011-03-21

申请人： Yoshinao SUZUKI ,  Yuui SHIMIZU

发明人： Yoshinao SUZUKI ,  Yuui SHIMIZU

IPC分类号： G11C5/02

CPC分类号： G11C5/02 ,  G11C5/04 ,  G11C16/06 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first memory chip, a second memory chip, and a control chip. The first chip includes a first inductor configured to transmit/receive a signal, and a memory cell. The second chip is disposed on the first chip and includes a second inductor configured to transmit/receive a signal, and a memory cell. The control chip includes a control circuit configured to control the first and second chips, and a third inductor configured to transmit/receive a signal to/from the first and second inductors. The outer peripheries of the first and second inductors are included in a closed space produced by extending the outer periphery of the third inductor in a direction perpendicular to a plane that includes the third inductor. The inductance of the third inductor is greater than at least one of the inductances of the first and second inductors.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一存储器芯片，第二存储器芯片和控制芯片。 第一芯片包括被配置为发送/接收信号的第一电感器和存储器单元。 第二芯片设置在第一芯片上，并且包括被配置为发送/接收信号的第二电感器和存储单元。 控制芯片包括被配置为控制第一和第二芯片的控制电路和被配置为向/从第一和第二电感器发送/接收信号的第三电感器。 第一和第二电感器的外围包括在通过使第三电感器的外周沿垂直于包括第三电感器的平面的方向延伸而产生的闭合空间。 第三电感器的电感大于第一和第二电感器的电感中的至少一个。

公开(公告)号：US20090067212A1

公开(公告)日：2009-03-12

申请号：US11846985

申请日：2007-08-29

申请人： Yuui SHIMIZU

发明人： Yuui SHIMIZU

IPC分类号： G11C11/21 ,  G11C11/02

CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/1673 ,  H01L27/24

摘要： A magnetic random access memory includes a memory element having a first fixed layer, a first recording layer, and a first nonmagnetic layer, a first reference element having a second fixed layer, a second recording layer, and a second nonmagnetic layer, antiparallel data being written in the first reference element, a second reference element making a pair with the first reference element, and having a third fixed layer, a third recording layer, and a third nonmagnetic layer, parallel data being written in the second reference element, and a current source which, when a read operation is performed, supplies a current from the second fixed layer to the second recording layer in the first reference element, and supplies the current from the third recording layer to the third fixed layer in the second reference element.

摘要翻译： 磁性随机存取存储器包括具有第一固定层，第一记录层和第一非磁性层的存储元件，具有第二固定层，第二记录层和第二非磁性层的第一参考元件，反平行数据 写入第一参考元素中的第二参考元素，与第一参考元素成对配对的第二参考元素，并具有第三固定层，第三记录层和第三非磁性层，并行数据被写入第二参考元素中，以及 电流源，当执行读取操作时，将来自第二固定层的电流提供给第一参考元件中的第二记录层，并将电流从第三记录层提供给第二参考元件中的第三固定层。