公开(公告)号：US20090003103A1

公开(公告)日：2009-01-01

申请号：US12142278

申请日：2008-06-19

申请人： Yuui SHIMIZU ,  Shigeo Ohshima ,  Mie Matsuo

发明人： Yuui SHIMIZU ,  Shigeo Ohshima ,  Mie Matsuo

IPC分类号： G11C5/14 ,  G11C8/00

CPC分类号： G11C5/145 ,  G11C5/04 ,  G11C5/066 ,  G11C5/143 ,  G11C16/30 ,  G11C29/12005 ,  G11C29/48 ,  G11C29/56 ,  G11C2029/5602 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/01019 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.

摘要翻译： 提供半导体器件，半导体存储器测试器和多芯片封装。 半导体器件包括多个非易失性半导体存储器; 升压电路，其产生用于操作所述多个非易失性半导体存储器的升压电压; 以及升压电路控制器，其基于所述多个非易失性半导体存储器的操作顺序来控制所述升压电路的操作以产生所述升压电压。

公开(公告)号：US08179730B2

公开(公告)日：2012-05-15

申请号：US12963247

申请日：2010-12-08

申请人： Yuui Shimizu ,  Shigeo Ohshima ,  Mie Matsuo

发明人： Yuui Shimizu ,  Shigeo Ohshima ,  Mie Matsuo

IPC分类号： G11C5/14 ,  G11C5/02 ,  G11C5/06 ,  H01L23/02 ,  H01L23/12 ,  H01L23/52

CPC分类号： G11C5/145 ,  G11C5/04 ,  G11C5/066 ,  G11C5/143 ,  G11C16/30 ,  G11C29/12005 ,  G11C29/48 ,  G11C29/56 ,  G11C2029/5602 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/01019 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.

摘要翻译： 提供半导体器件，半导体存储器测试器和多芯片封装。 半导体器件包括多个非易失性半导体存储器; 升压电路，其产生用于操作所述多个非易失性半导体存储器的升压电压; 以及升压电路控制器，其基于所述多个非易失性半导体存储器的操作顺序来控制所述升压电路的操作以产生所述升压电压。

公开(公告)号：US20110074494A1

公开(公告)日：2011-03-31

申请号：US12963247

申请日：2010-12-08

申请人： Yuui Shimizu ,  Shigeo Ohshima ,  Mie Matsuo

发明人： Yuui Shimizu ,  Shigeo Ohshima ,  Mie Matsuo

IPC分类号： G05F1/10

CPC分类号： G11C5/145 ,  G11C5/04 ,  G11C5/066 ,  G11C5/143 ,  G11C16/30 ,  G11C29/12005 ,  G11C29/48 ,  G11C29/56 ,  G11C2029/5602 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/01019 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.

摘要翻译： 提供半导体器件，半导体存储器测试器和多芯片封装。 半导体器件包括多个非易失性半导体存储器; 升压电路，其产生用于操作所述多个非易失性半导体存储器的升压电压; 以及升压电路控制器，其基于所述多个非易失性半导体存储器的操作顺序来控制所述升压电路的操作以产生所述升压电压。

公开(公告)号：US07869240B2

公开(公告)日：2011-01-11

申请号：US12142278

申请日：2008-06-19

申请人： Yuui Shimizu ,  Shigeo Ohshima ,  Mie Matsuo

发明人： Yuui Shimizu ,  Shigeo Ohshima ,  Mie Matsuo

IPC分类号： G11C5/02 ,  G11C5/06 ,  H01L23/52

CPC分类号： G11C5/145 ,  G11C5/04 ,  G11C5/066 ,  G11C5/143 ,  G11C16/30 ,  G11C29/12005 ,  G11C29/48 ,  G11C29/56 ,  G11C2029/5602 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2225/06506 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/01019 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories.

摘要翻译： 提供半导体器件，半导体存储器测试器和多芯片封装。 半导体器件包括多个非易失性半导体存储器; 升压电路，其产生用于操作所述多个非易失性半导体存储器的升压电压; 以及升压电路控制器，其基于所述多个非易失性半导体存储器的操作顺序来控制所述升压电路的操作以产生所述升压电压。

公开(公告)号：US08580652B2

公开(公告)日：2013-11-12

申请号：US12875628

申请日：2010-09-03

申请人： Atsuko Kawasaki ,  Kenichiro Hagiwara ,  Ikuko Inoue ,  Kazutaka Akiyama ,  Itsuko Sakai ,  Mie Matsuo ,  Masahiro Sekiguchi ,  Yoshiteru Koseki ,  Hiroki Neko ,  Koushi Tozuka ,  Kazuhiko Nakadate ,  Takuto Inoue

发明人： Atsuko Kawasaki ,  Kenichiro Hagiwara ,  Ikuko Inoue ,  Kazutaka Akiyama ,  Itsuko Sakai ,  Mie Matsuo ,  Masahiro Sekiguchi ,  Yoshiteru Koseki ,  Hiroki Neko ,  Koushi Tozuka ,  Kazuhiko Nakadate ,  Takuto Inoue

IPC分类号： H01L29/78

CPC分类号： H01L27/14683 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/522 ,  H01L24/13 ,  H01L24/32 ,  H01L27/14618 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12043 ,  H01L2924/3025 ,  H01L2924/00

摘要： According to one embodiment, a manufacturing method of a semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate having first and second main surfaces, and a through hole passing through between the first and second main surfaces, a pad on the first main surface, a through electrode in the through hole, and a connection structure including a connection portion to directly connect the pad and the through electrode, and another connection portion to indirectly connect the pad and the through electrode. The method includes forming an isolation region in the first main surface, the isolation region being in a region where the through electrode is to be formed and being in a region other than the region where the through hole is to be formed, forming the pad, and forming the through hole by processing the substrate to expose a part of the pad.

摘要翻译： 根据一个实施例，公开了一种半导体器件的制造方法。 半导体器件包括具有第一和第二主表面的半导体衬底，以及穿过第一和第二主表面之间的通孔，第一主表面上的焊盘，通孔中的通孔，以及包括 连接部分，以直接连接焊盘和通孔，以及另一个连接部分，以间接连接焊盘和通孔。 该方法包括在第一主表面中形成隔离区，隔离区位于要形成通孔的区域中，并且位于除了形成通孔的区域之外的区域中，形成垫， 以及通过处理所述衬底形成所述通孔以暴露所述衬垫的一部分。

公开(公告)号：US08098312B2

公开(公告)日：2012-01-17

申请号：US12404675

申请日：2009-03-16

申请人： Mie Matsuo ,  Sachiyo Ito

发明人： Mie Matsuo ,  Sachiyo Ito

IPC分类号： H04N3/14 ,  H04N5/225

CPC分类号： H01L27/14636 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L2924/0002 ,  H04N5/2257 ,  H04N5/374 ,  H01L2924/00

摘要： A solid-state image pickup apparatus includes an image pickup pixel unit in which a plurality of pixels each including a photoelectric conversion element and a field-effect transistor are arranged on a semiconductor substrate so that a light-receiving surface is disposed at a first surface side of the semiconductor substrate; a peripheral circuit unit provided at a periphery of the image pickup pixel unit of the semiconductor substrate; and a multilayered wiring layer in which a plurality of wiring layers for driving the field-effect transistor of the image pickup pixel unit are laminated at a second surface side of the semiconductor substrate, wherein a wiring in each of the wiring layers constituting the multilayered wiring layer is disposed so that a coverage of the wiring located at least in the image pickup pixel unit of the semiconductor substrate reaches 100%, viewed from the second surface side.

摘要翻译： 固态图像拾取装置包括：图像拾取像素单元，其中包括光电转换元件和场效应晶体管的多个像素布置在半导体衬底上，使得光接收表面设置在第一表面 侧; 设置在半导体衬底的摄像像素单元的周围的外围电路单元; 以及多层布线层，其中用于驱动图像拾取像素单元的场效应晶体管的多个布线层层叠在半导体基板的第二表面侧，其中构成多层布线的每个布线层中的布线 从第二表面侧观察，使至少位于半导体衬底的摄像像素单元中的配线的覆盖范围达到100％。

公开(公告)号：US07859073B2

公开(公告)日：2010-12-28

申请号：US12166810

申请日：2008-07-02

申请人： Mie Matsuo ,  Yusuke Kohyama

发明人： Mie Matsuo ,  Yusuke Kohyama

IPC分类号： H01L31/0203

CPC分类号： H01L27/14618 ,  H01L24/24 ,  H01L27/1464 ,  H01L2224/13 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/12043 ,  H04N5/2257 ,  H01L2924/00014 ,  H01L2924/00

摘要： The present invention provides a solid-state image pickup device including an image pickup pixel section which is provided on a semiconductor substrate and in which a plurality of pixels each having a photoelectric conversion element and a field-effect transistor are arranged, and a peripheral circuit section for the image pickup pixel section. An interconnect layer driving the field-effect transistor in the image pickup pixel section is formed on a first surface side of the semiconductor substrate. A light receiving surface of the photoelectric conversion element is located on a second surface side of the semiconductor substrate. The solid-state image pickup device includes a first terminal exposed from the second surface side of the semiconductor substrate, and a second terminal electrically connected to the first terminal and connectable to an external device on the first surface side of the semiconductor substrate.

摘要翻译： 本发明提供了一种固态摄像装置，包括：设置在半导体衬底上的摄像像素部分，其中配置有多个具有光电转换元件和场效应晶体管的像素;以及外围电路 图像拾取像素部分。 驱动图像拾取像素部中的场效应晶体管的互连层形成在半导体衬底的第一表面侧上。 光电转换元件的光接收表面位于半导体衬底的第二表面侧。 固态摄像装置包括从半导体衬底的第二表面侧露出的第一端子和与第一端子电连接并可连接到半导体衬底的第一表面侧上的外部器件的第二端子。

公开(公告)号：US07507634B2

公开(公告)日：2009-03-24

申请号：US11812490

申请日：2007-06-19

申请人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

发明人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

IPC分类号： H01L21/764 ,  H01L27/12

CPC分类号： H01L27/10805 ,  B82Y20/00 ,  G02B6/122 ,  G02B6/1225 ,  G02B2006/12097 ,  H01L21/3247 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78639

摘要： To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

摘要翻译： 通过在半导体衬底的表面上二维地形成沟槽，然后对半导体衬底进行热处理，将多个沟槽改变为一个平坦的空间。

公开(公告)号：US07235456B2

公开(公告)日：2007-06-26

申请号：US11340594

申请日：2006-01-27

申请人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

发明人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

IPC分类号： H01L21/764 ,  H01L27/12

CPC分类号： H01L27/10805 ,  B82Y20/00 ,  G02B6/122 ,  G02B6/1225 ,  G02B2006/12097 ,  H01L21/3247 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78639

摘要： To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

摘要翻译： 通过在半导体衬底的表面上二维地形成沟槽，然后对半导体衬底进行热处理，将多个沟槽改变为一个平坦的空间。

公开(公告)号：US07095112B2

公开(公告)日：2006-08-22

申请号：US10664150

申请日：2003-09-17

申请人： Mitsuyoshi Endo ,  Mie Matsuo ,  Chiaki Takubo

发明人： Mitsuyoshi Endo ,  Mie Matsuo ,  Chiaki Takubo

IPC分类号： H01L23/48 ,  H05K7/02 ,  H01L27/02

CPC分类号： H01L23/66 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided a semiconductor device including: a wiring board; a semiconductor chip having a pad electrically connected to a wiring on the wiring board; a second semiconductor chip provided on the wiring board at a position facing a side of the semiconductor chip, having passive elements integrated therein, and having pads for external connection to which both ends of the passive elements are connected respectively and at least one of which is electrically connected to the wiring on the wiring board electrically connected to the pad of the semiconductor chip.

摘要翻译： 提供一种半导体器件，包括：布线板; 半导体芯片，其具有电连接到所述布线板上的布线的焊盘; 第二半导体芯片，其设置在面对半导体芯片的一侧的位置处的布线板上，其中集成有无源元件，并且具有用于外部连接的焊盘，无源元件的两端分别连接到该衬垫，并且其中至少一个是 电连接到电连接到半导体芯片的焊盘的布线板上的布线。