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    Semiconductor device including I/O oxide nitrided core oxide on substrate, and method of manufacture
    6.
    发明申请
    Semiconductor device including I/O oxide nitrided core oxide on substrate, and method of manufacture 有权
    在衬底上包括I / O氧化物氮化核心氧化物的半导体器件及其制造方法

    公开(公告)号：US20110081758A1

    公开(公告)日：2011-04-07

    申请号：US12923889

    申请日：2010-10-13

    申请人： Zhen-Cheng Wu ,  Yung-Cheng Lu ,  Pi-Tsung Chen ,  Ying-Tsung Chen

    发明人： Zhen-Cheng Wu ,  Yung-Cheng Lu ,  Pi-Tsung Chen ,  Ying-Tsung Chen

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823462 ,  H01L27/088 ,  Y10S438/981

    摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.

    摘要翻译： 半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的核心区域和用于外围电路的外围区域。 半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物 ，以及I / O氧化物上的第二多晶硅图案。

    Method for planarizing semiconductor structures
    8.
    发明授权
    Method for planarizing semiconductor structures 有权

    公开(公告)号：US07247571B2

    公开(公告)日：2007-07-24

    申请号：US11226979

    申请日：2005-09-15

    申请人： Ying-Tsung Chen ,  Yung-Cheng Lu ,  Zhen-Cheng Wu ,  Pi-Tsung Chen

    发明人： Ying-Tsung Chen ,  Yung-Cheng Lu ,  Zhen-Cheng Wu ,  Pi-Tsung Chen

    IPC分类号： H01L21/311

    CPC分类号： H01L21/31053 ,  H01L22/20

    摘要： A method for planarizing a semiconductor structure is disclosed. A semiconductor substrate having a first area in which one or more trenches are formed in a first pattern density, and a second area in which one or more trenches are formed in a second pattern density lower than the first pattern density, is provided. A first dielectric layer is formed above the semiconductor for covering the trenches in the first and second areas. A first chemical mechanical polishing is performed on the first dielectric layer using a predetermined type of slurry for reducing a thickness thereof. The first dielectric layer is then rinsed. A second chemical mechanical polishing is performed on the first dielectric layer using the predetermined type of slurry for further removing the first dielectric layer outside the trenches, thereby reducing a step height variation between surfaces of the first and second areas.

    Semiconductor device including I/O oxide and nitrided core oxide on substrate, and method of manufacture
    9.
    发明申请
    Semiconductor device including I/O oxide and nitrided core oxide on substrate, and method of manufacture 有权
    在衬底上包括I / O氧化物和氮化核心氧化物的半导体器件及其制造方法

    公开(公告)号：US20070013009A1

    公开(公告)日：2007-01-18

    申请号：US11181915

    申请日：2005-07-15

    申请人： Zhen-Cheng Wu ,  Yung-Cheng Lu ,  Pi-Tsung Chen ,  Ying-Tsung Chen

    发明人： Zhen-Cheng Wu ,  Yung-Cheng Lu ,  Pi-Tsung Chen ,  Ying-Tsung Chen

    IPC分类号： H01L29/78 ,  H01L21/8234

    CPC分类号： H01L21/823462 ,  H01L27/088 ,  Y10S438/981

    摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.

    摘要翻译： 半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的核心区域和用于外围电路的外围区域。 半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物 ，以及I / O氧化物上的第二多晶硅图案。

    Post-ESL porogen burn-out for copper ELK integration
    10.
    发明授权
    Post-ESL porogen burn-out for copper ELK integration 有权
    用于铜ELK整合的后ESL致孔剂烧尽

    公开(公告)号：US07217648B2

    公开(公告)日：2007-05-15

    申请号：US11020372

    申请日：2004-12-22

    申请人： Yung-Cheng Lu ,  Ying-Tsung Chen ,  Zhen-Cheng Wu ,  Pi-Tsung Chen

    发明人： Yung-Cheng Lu ,  Ying-Tsung Chen ,  Zhen-Cheng Wu ,  Pi-Tsung Chen

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31695 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L2221/1047

    摘要： A method of manufacturing a semiconductor device having a porous, low-k dielectric layer is provided. A preferred embodiment comprises the steps of forming a porogen-containing, low-k dielectric layer, in the damascene process. In preferred embodiments, pore generation, by e-beam porogen degradation, occurs after the steps of CMP planarizing the damascene copper conductor and depositing a semipermeable cap layer. In alternative embodiments, the cap layer consists essentially of silicon carbide, silicon nitride, Co, W, Al, Ta, Ti, Ni, Ru, and combinations thereof. The semipermeable cap layer is preferably deposited under PECVD conditions such that the cap layer is sufficiently permeable to enable removal of porogen degradation by-products. Preferred embodiments further include an in-situ N2/NH3 treatment before depositing the semipermeable cap layer.

    摘要翻译： 提供一种制造具有多孔低k电介质层的半导体器件的方法。 优选的实施方案包括在镶嵌工艺中形成含致孔剂的低k电介质层的步骤。 在优选的实施方案中，通过电子束致孔剂降解的孔产生在CMP平坦化镶嵌铜导体并沉积半透膜盖层的步骤之后发生。 在替代实施例中，盖层基本上由碳化硅，氮化硅，Co，W，Al，Ta，Ti，Ni，Ru及其组合组成。 半透膜盖层优选在PECVD条件下沉积，使得盖层具有足够的可渗透性以能够除去致孔剂降解副产物。 优选实施方案还包括在沉积半透膜盖层之前的原位N 2 / NH 3 N 3处理。