公开(公告)号：US07919848B2

公开(公告)日：2011-04-05

申请号：US11833898

申请日：2007-08-03

申请人： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Abelardo Jr Hadap Advincula ,  Lionel Chien Hui Tay

发明人： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Abelardo Jr Hadap Advincula ,  Lionel Chien Hui Tay

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L23/49548 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： An integrated circuit package system includes: forming a die-attach paddle, an outer interconnect, and an inner interconnect toward the die-attach paddle beyond the outer interconnect; mounting an integrated circuit device over the die-attach paddle; connecting the integrated circuit device to the inner interconnect and the outer interconnect; encapsulating the integrated circuit device over the die-attach paddle; attaching an external interconnect under the outer interconnect; and attaching a circuit device under the die-attach paddle and extended laterally beyond opposite sides of the die-attach paddle.

摘要翻译： 集成电路封装系统包括：形成管芯附接焊盘，外部互连和内部互连，使芯片附着焊盘超出外部互连; 将集成电路装置安装在芯片附接板上; 将集成电路装置连接到内部互连和外部互连; 将所述集成电路器件封装在所述管芯附接焊盘上; 在外部互连下方附加外部互连; 以及将电路装置附接在所述管芯附接桨下方并且横向延伸超过所述管芯附着桨的相对侧。

公开(公告)号：US07785929B2

公开(公告)日：2010-08-31

申请号：US12054682

申请日：2008-03-25

申请人： Zigmund Ramirez Camacho ,  Abelardo Jr. Hadap Advincula ,  Henry Descalzo Bathan ,  Lionel Chien Hui Tay

发明人： Zigmund Ramirez Camacho ,  Abelardo Jr. Hadap Advincula ,  Henry Descalzo Bathan ,  Lionel Chien Hui Tay

IPC分类号： H01L21/44

CPC分类号： H01L23/49575 ,  H01L23/3135 ,  H01L23/49537 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention provides a mountable integrated circuit package system comprising: providing an inner integrated circuit package including a first external interconnect having a shoulder; connecting an intraconnect between a second external interconnect and the shoulder; and forming an outer encapsulation over the inner integrated circuit package, the intraconnect, and partially exposing the first external interconnect on a top encapsulation side of the outer encapsulation and the second external interconnect on a bottom encapsulation side of the outer encapsulation.

摘要翻译： 本发明提供一种可安装的集成电路封装系统，包括：提供内部集成电路封装，其包括具有肩部的第一外部互连; 连接第二外部互连和肩部之间的连接; 以及在所述内部集成电路封装上形成外部封装，在所述外部封装的底部封装侧上将所述外部封装的顶部封装侧上的所述第一外部互连和所述第二外部互连部分地暴露于所述第一外部互连。

公开(公告)号：US08957515B2

公开(公告)日：2015-02-17

申请号：US11936516

申请日：2007-11-07

申请人： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Abelardo Jr. Hadap Advincula ,  Lionel Chien Hui Tay

发明人： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Abelardo Jr. Hadap Advincula ,  Lionel Chien Hui Tay

IPC分类号： H01L23/48 ,  H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/49548 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package system includes: forming an array of external interconnects with an intersecting region between the external interconnects; removing the intersecting region for forming an isolation hole between the external interconnects; mounting an integrated circuit die over the external interconnects; connecting an internal interconnect between the integrated circuit die and the external interconnects; and forming a package encapsulation over the integrated circuit die with the external interconnects partially exposed.

摘要翻译： 集成电路封装系统包括：形成具有外部互连之间的相交区域的外部互连阵列; 去除用于在外部互连之间形成隔离孔的交叉区域; 在外部互连上安装集成电路管芯; 连接集成电路管芯和外部互连件之间的内部互连; 以及在所述集成电路管芯上形成封装封装，所述外部互连部分露出。

公开(公告)号：US09059074B2

公开(公告)日：2015-06-16

申请号：US12055526

申请日：2008-03-26

申请人： Zigmund Ramirez Camacho ,  Lionel Chien Hui Tay ,  Henry Descalzo Bathan ,  Abelardo Jr. Hadap Advincula

发明人： Zigmund Ramirez Camacho ,  Lionel Chien Hui Tay ,  Henry Descalzo Bathan ,  Abelardo Jr. Hadap Advincula

IPC分类号： H01L23/02 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/495 ,  H01L29/04

CPC分类号： H01L24/19 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49524 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24247 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

摘要： An integrated circuit package system includes: mounting an integrated circuit die adjacent to a lead; forming a first encapsulation around and exposing the integrated circuit die and the lead; and forming a planar interconnect between the integrated circuit die and the lead with the planar interconnect on the first encapsulation.

摘要翻译： 集成电路封装系统包括：将集成电路模具安装在与引线相邻的位置; 围绕并暴露集成电路管芯和引线而形成第一封装; 以及在所述第一封装上利用所述平面互连件在所述集成电路管芯和所述引线之间形成平面互连。

公开(公告)号：US08067825B2

公开(公告)日：2011-11-29

申请号：US11863700

申请日：2007-09-28

申请人： Abelardo Jr. Hadap Advincula ,  Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Jairus Legaspi Pisigan

发明人： Abelardo Jr. Hadap Advincula ,  Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Jairus Legaspi Pisigan

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/49503 ,  H01L24/28 ,  H01L24/29 ,  H01L24/31 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05554 ,  H01L2224/2919 ,  H01L2224/29288 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package system includes providing die; forming leads adjacent the die; forming a die paddle adjacent the leads with the die thereover; and forming a cavity for isolating one of the die and a die attach segment of the die paddle.

摘要翻译： 集成电路封装系统包括提供裸片; 在模具附近形成引线; 在其上与模具形成邻近引线的芯片; 以及形成用于隔离所述管芯和所述管芯焊盘的管芯附接部分中的一个的腔。

公开(公告)号：US08941219B2

公开(公告)日：2015-01-27

申请号：US13080469

申请日：2011-04-05

申请人： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Lionel Chien Hui Tay ,  Jairus Legaspi Pisigan

发明人： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Lionel Chien Hui Tay ,  Jairus Legaspi Pisigan

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10

CPC分类号： H01L23/49551 ,  H01L21/4828 ,  H01L23/3107 ,  H01L23/495 ,  H01L24/16 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/85455 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/013 ,  H01L2924/00012 ,  H01L2224/0401

摘要： An integrated circuit package system includes: interconnection pads; a first device mounted below the interconnection pads; a bond wire, or a solder ball connecting the first device to the interconnection pads; a lead connected to the interconnection pad or to the first device; an encapsulation having a top surface encapsulating the first device; and a recess in the top surface of the encapsulation with the interconnection pads exposed therefrom.

摘要翻译： 集成电路封装系统包括：互连焊盘; 安装在互连焊盘下方的第一器件; 接合线或将第一器件连接到互连焊盘的焊球; 连接到互连衬垫或第一器件的引线; 封装，其具有封装所述第一器件的顶表面; 以及在封装的顶表面中的凹槽，其中互连焊盘从其暴露。

公开(公告)号：US08937393B2

公开(公告)日：2015-01-20

申请号：US11744062

申请日：2007-05-03

申请人： Henry Descalzo Bathan ,  Zigmund Ramirez Camacho ,  Lionel Chien Hui Tay ,  Frederick Rodriguez Dahilig

发明人： Henry Descalzo Bathan ,  Zigmund Ramirez Camacho ,  Lionel Chien Hui Tay ,  Frederick Rodriguez Dahilig

IPC分类号： H01L21/683 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00

CPC分类号： H01L23/49575 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/48 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package system is provided including connecting an integrated circuit die with an external interconnect, forming a first encapsulation having a device cavity with the integrated circuit die therein, mounting a device in the device cavity over the integrated circuit die, and forming a cover over the device and the first encapsulation.

摘要翻译： 提供一种集成电路封装系统，包括将集成电路管芯与外部互连件连接，形成具有集成电路管芯的器件空腔的第一封装，将器件腔中的器件安装在集成电路管芯上，并形成覆盖层 通过设备和第一次封装。

公开(公告)号：US08692377B2

公开(公告)日：2014-04-08

申请号：US13069744

申请日：2011-03-23

申请人： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Lionel Chien Hui Tay

发明人： Zigmund Ramirez Camacho ,  Henry Descalzo Bathan ,  Lionel Chien Hui Tay

IPC分类号： H01L23/498

CPC分类号： H01L24/97 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49582 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： An integrated circuit packaging system and method of manufacture thereof includes: an L-plated lead; a die conductively connected to the L-plated lead; and an encapsulant encapsulating the L-plated lead and the die.

摘要翻译： 集成电路封装系统及其制造方法包括：镀L引线; 导电地连接到L镀层导线的模具; 以及封装L镀层引线和芯片的密封剂。

公开(公告)号：US08592252B2

公开(公告)日：2013-11-26

申请号：US12858593

申请日：2010-08-18

申请人： Henry Descalzo Bathan ,  Zigmund Ramirez Camacho ,  Lionel Chien Hui Tay ,  Arnel Senosa Trasporto

发明人： Henry Descalzo Bathan ,  Zigmund Ramirez Camacho ,  Lionel Chien Hui Tay ,  Arnel Senosa Trasporto

IPC分类号： H01L21/50 ,  H01L21/78

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/82001 ,  H01L2224/82039 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00

摘要： A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.

公开(公告)号：US08536690B2

公开(公告)日：2013-09-17

申请号：US12564852

申请日：2009-09-22

申请人： Zigmund Ramirez Camacho ,  Lionel Chien Hui Tay ,  Henry Descalzo Bathan ,  Guruprasad Badakere Govindaiah

发明人： Zigmund Ramirez Camacho ,  Lionel Chien Hui Tay ,  Henry Descalzo Bathan ,  Guruprasad Badakere Govindaiah

IPC分类号： H01L23/495

CPC分类号： H01L24/48 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/5286 ,  H01L24/29 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A method of manufacture of an integrated circuit packaging system includes: attaching a semiconductor die to a die pad of a leadframe; forming a cap layer on top of the semiconductor die for acting as a ground plane or a power plane; and connecting the semiconductor die to the cap layer through a cap bonding wire.

摘要翻译： 一种集成电路封装系统的制造方法，包括：将半导体管芯附接到引线框架的管芯焊盘; 在所述半导体管芯的顶部上形成盖层，用作接地层或电源层; 以及通过盖接合线将半导体管芯连接到盖层。