公开(公告)号：US5930232A

公开(公告)日：1999-07-27

申请号：US612982

申请日：1996-03-01

申请人： Douglas W. Miller

发明人： Douglas W. Miller

IPC分类号： H04Q3/545 ,  H04J1/16 ,  H04J3/16

CPC分类号： H04Q3/54533 ,  H04Q2213/13093 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13167 ,  H04Q2213/13204

摘要： Method and system for implementing a protection switching protocol of a telecommunications network (14). The method and system employs a protection object (80) including a set of attributes (84) and a set of functions (86) in communication with the attributes (84). The attributes (84) may store switching state information of the telecommunications network (14). The functions (86) may include a set of service functions (88) and a set of private functions (90). The service functions (88) may accept switching state information of the telecommunications network (14), store that information to the attributes (84) and retrieved that information from the attributes (84). The private functions (90) may also retrieved switching state information from the attributes (84). The private functions (90) may be invoked by a service function (88) or by another private function (90). Together, the service functions (88) and the private functions (90) implement the predefined protection switching protocol and invoke a set of system functions (100). The system functions (100) effect switching operations of the telecommunications network (14).

摘要翻译： 用于实现电信网络（14）的保护交换协议的方法和系统。 所述方法和系统采用包括与属性（84）通信的一组属性（84）和一组函数（86）的保护对象（80）。 属性（84）可以存储电信网络（14）的切换状态信息。 功能（86）可以包括一组服务功能（88）和一组私有功能（90）。 服务功能（88）可以接受电信网络（14）的交换状态信息，将该信息存储到属性（84），并且从属性（84）检索该信息。 私有功能（90）还可以从属性（84）检索切换状态信息。 私有功能（90）可由服务功能（88）或另一专用功能（90）调用。 一起，服务功能（88）和私有功能（90）实现预定义的保护切换协议并且调用一组系统功能（100）。 系统功能（100）影响电信网络（14）的切换操作。

公开(公告)号：US5872780A

公开(公告)日：1999-02-16

申请号：US886724

申请日：1992-05-21

申请人： Sahabettin C. Demiray ,  Dale L. Krisher ,  William B. Weeber

发明人： Sahabettin C. Demiray ,  Dale L. Krisher ,  William B. Weeber

IPC分类号： H04J3/14 ,  H04J3/16 ,  H04Q11/04 ,  H04L12/52

CPC分类号： H04J3/14 ,  H04J3/1611 ,  H04J2203/006 ,  Y10S370/907

摘要： An internal signal within a SONET element has a transport format having overhead and payload mapped in a manner similar to the Synchronous Optical Network standard mapping, except having selected overhead bytes defined differently, including a byte used for communicating odd parity calculated over an odd number of bytes of a frame of the transport format to determine correct or incorrect parity, selected bytes used for inter-module automatic protection switching, and a pointer having a selected fixed value, along with an adjusted virtual tributary pointer in a virtual tributary mode.

摘要翻译： SONET元件内的内部信号具有以类似于同步光网络标准映射的方式映射的开销和有效载荷的传输格式，除了具有不同定义的所选开销字节之外，包括用于传送在奇数个 传输格式的帧的字节以确定正确或不正确的奇偶校验，用于模块间自动保护切换的所选字节，以及具有选定的固定值的指针以及虚拟辅助模式中调整的虚拟辅助指针。

公开(公告)号：US5790614A

公开(公告)日：1998-08-04

申请号：US675649

申请日：1996-07-02

申请人： William E. Powell

发明人： William E. Powell

IPC分类号： H03L7/099 ,  H03L7/18 ,  H03L7/197 ,  H03L7/23 ,  H04L7/033 ,  H03D3/24

CPC分类号： H03L7/1978 ,  H03L7/0994 ,  H03L7/1806 ,  H03L7/235 ,  H04L7/0331 ,  H04L7/0334

摘要： Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.

公开(公告)号：US5778447A

公开(公告)日：1998-07-07

申请号：US856347

申请日：1997-05-14

申请人： David W. Kuddes

发明人： David W. Kuddes

IPC分类号： G06F12/02 ,  G06F13/16 ,  G06F12/06

CPC分类号： G06F13/161 ,  G06F12/0215 ,  Y02B60/1225 ,  Y02B60/1228

摘要： A data processing system including dynamic random access memory (DRAM) in a bus architecture is disclosed. A controller is included in the system which unconditionally generates the row address strobe (RAS.sub.--) and column address strobe (CAS.sub.--) signals to the DRAM responsive to the initiation of a bus cycle. The controller also includes a decoder which decodes the address value during the DRAM cycle initiated by the RAS.sub.-- and CAS.sub.-- signals, and generates the select signals (for example, output enable and write enable signals, depending upon whether the access is a read or a write) if the address value indicates that the bus operation is to be a DRAM access. No select signal is generated in the event that the bus operation is not a DRAM access, so that the DRAM operation initiated by the RAS.sub.-- and CAS.sub.-- signals remains an internal operation and does not affect the common data bus. The effective DRAM system cycle time is reduced because all bus operations assume that the operation is a DRAM access; no DRAM access is delayed by the decoding of the address value.

摘要翻译： 公开了一种包括总线架构中的动态随机存取存储器（DRAM）的数据处理系统。 系统中包括一个控制器，无线产生响应总线周期启动的行地址选通（RAS-）和列地址选通（CAS-）信号给DRAM。 该控制器还包括解码器，其在由RAS和CAS信号发起的DRAM周期期间解码地址值，并且根据访问是读取还是生成选择信号（例如，输出使能和写使能信号） 写入），如果地址值表示总线操作是DRAM访问。 在总线操作不是DRAM访问的情况下不产生选择信号，使得由RAS和CAS信号启动的DRAM操作保持内部操作并且不影响公共数据总线。 有效的DRAM系统周期时间减少，因为所有总线操作都假定操作是DRAM访问; 通过地址值的解码不会延迟DRAM访问。

公开(公告)号：US5754607A

公开(公告)日：1998-05-19

申请号：US439091

申请日：1995-05-10

申请人： William E. Powell ,  David T. Hayes

发明人： William E. Powell ,  David T. Hayes

IPC分类号： H03L7/093 ,  H03L7/14 ,  H03L7/199 ,  H04L7/00 ,  H04L7/033 ,  H04Q11/04 ,  H03D3/24

CPC分类号： H03L7/093 ,  H03L7/146 ,  H03L7/199 ,  H04J2203/006 ,  H04L7/0083 ,  H04L7/0331 ,  Y10S331/02

摘要： A method and an apparatus are provided to achieve fast phase settling when a reference signal for a phase locked loop changes from a first frequency to a second frequency, such as during holdover recovery in a synchronous optical network. The present method acquires the second frequency with a phase locked loop (24). After the frequency is acquired, the integral register (39) of the phase locked loop (24) is loaded with the contents of the output frequency register (34) of the phase locked loop (24). The phase detector (28) of the phase locked loop (24) is then realigned to the reference signal.

摘要翻译： 提供了一种方法和装置，用于当用于锁相环的参考信号从第一频率变为第二频率（例如在同步光网络中的保持恢复期间）期间实现快速相位稳定。 本方法利用锁相环获得第二频率（24）。 在获取频率之后，锁相环（24）的积分寄存器（39）加载锁相环（24）的输出频率寄存器（34）的内容。 然后将锁相环（24）的相位检测器（28）重新对准参考信号。

公开(公告)号：US5721424A

公开(公告)日：1998-02-24

申请号：US660867

申请日：1996-06-10

申请人： Alistair J. Price

发明人： Alistair J. Price

IPC分类号： H01L31/02 ,  H01J40/14

CPC分类号： H01L31/02027

摘要： An photodetector circuit comprising an avalanche photodiode having a signal input for receiving an input optical signal to be converted to an electrical signal. The photodetector circuit further includes biasing circuitry, coupled to the avalanche photodiode, for applying a bias voltage to the avalanche diode. The bias circuitry includes: (1) a dc bias circuit for providing a dc component to the bias voltage for maintaining the avalanche diode in a stable avalanche gain condition when receiving the input optical signal; and (2) a modulating circuit for providing a high frequency modulating component to the bias voltage for modulating the bias voltage in a manner that enhances the operational characteristics of the avalanche photodiode. In particular, the modulating component to the bias voltage decrease the noise of the signal output of the avalanche photodiode for a given average gain, and increases the bandwidth of the signal output of the avalanche photodiode for a given average gain.

摘要翻译： 一种光电检测器电路，其包括雪崩光电二极管，其具有用于接收要转换为电信号的输入光信号的信号输入。 光电检测器电路还包括耦合到雪崩光电二极管的偏置电路，用于向雪崩二极管施加偏置电压。 偏置电路包括：（1）直流偏置电路，用于在接收输入光信号时向直流分量提供偏置电压，以将雪崩二极管保持在稳定的雪崩增益状态; 以及（2）调制电路，用于以增加雪崩光电二极管的操作特性的方式将偏置电压提供给偏置电压来调制偏置电压。 特别地，对于给定的平均增益，偏置电压的调制分量降低了雪崩光电二极管的信号输出的噪声，并且为给定的平均增益增加了雪崩光电二极管的信号输出的带宽。

公开(公告)号：US5612862A

公开(公告)日：1997-03-18

申请号：US238779

申请日：1994-05-06

申请人： C. Lee Marusik ,  Edward Johnson

发明人： C. Lee Marusik ,  Edward Johnson

IPC分类号： H02M3/335

CPC分类号： H02M3/33561 ,  Y10S323/901

摘要： Magnetic amplifier post regulator (54) includes magnetic amplifier (42) that has a main magnetic amplifier winding, reset transistor (76), error amplifier (58), and auxiliary magnetic amplifier winding (220). Magnetic amplifier (42) controllably blocks a portion of the input voltage N.sub.s /N.sub.p V.sub.IN from winding (30) of transformer (18) in response to a controlled resetting condition and produces therefrom a magnetic amplifier output voltage (v.sub.2). Auxiliary output circuit (14) uses the magnetic amplifier (42) output voltage (v.sub.2) to produce the desired auxiliary output voltage (V.sub.OS). Reset transistor (76) controls reset current to magnetic amplifier (42) in response to an error signal from error amplifier (58). Error amplifier (58) compares auxiliary output voltage (V.sub.OS) to predetermined reference voltage (66) and generates the error signal from the comparison. Auxiliary magnetic amplifier winding (220) has a predetermined number of turns (N.sub.2) on magnetic amplifier (42) and increases the dynamic range of magnetic amplifier post regulator (54) for controlling reset transistor (76) and auxiliary output circuit (14) so that auxiliary output voltage (V.sub.OS) may attain a zero value while reset transistor (76) controls magnetic amplifier (42) in a blocking state (T.sub.B) during the entire on-time (T.sub.ON) of power switch transistor (24) of primary circuit (16).

摘要翻译： 磁放大器后调节器（54）包括具有主磁放大器绕组，复位晶体管（76），误差放大器（58）和辅助磁放大器绕组（220）的磁放大器（42）。 磁放大器（42）响应于受控的复位条件可控制地阻挡输入电压Ns / Np VIN的一部分从变压器（18）的绕组（30）产生磁放大器输出电压（v2）。 辅助输出电路（14）使用磁放大器（42）输出电压（v2）产生所需的辅助输出电压（VOS）。 响应于来自误差放大器（58）的误差信号，复位晶体管（76）控制到磁放大器（42）的复位电流。 误差放大器（58）将辅助输出电压（VOS）与预定参考电压（66）进行比较，并从比较中产生误差信号。 辅助磁放大器绕组（220）在磁放大器（42）上具有预定的匝数（N2），并且增加用于控制复位晶体管（76）和辅助输出电路（14）的磁放大器后调节器（54）的动态范围 在主电路的功率开关晶体管（24）的整个导通时间（TON）期间，复位晶体管（76）控制处于阻塞状态（TB）的磁放大器（42）的辅助输出电压（VOS）可以达到零值 （16）。

公开(公告)号：US5594576A

公开(公告)日：1997-01-14

申请号：US384377

申请日：1995-02-03

申请人： Joseph E. Sutherland ,  Paul M. Matsumura

发明人： Joseph E. Sutherland ,  Paul M. Matsumura

IPC分类号： H04B10/272 ,  H04J14/02 ,  H04J14/08 ,  H04Q11/00 ,  H04B10/20

CPC分类号： H04Q11/0067 ,  H04J14/0298 ,  H04J14/086 ,  H04J2203/0026 ,  H04J2203/0041 ,  H04J2203/0046 ,  H04J2203/0078 ,  H04J2203/008 ,  H04Q11/0071 ,  H04Q2213/1301 ,  H04Q2213/1332 ,  H04Q2213/13322

摘要： In an optical fiber transmission network, a remote terminal fed by a high-rate optical signal includes an internal electrical link called a serial interface bus carrying 24 DS0 channels. The optical transmission network is extended by converting the SBI baseband signal from electrical to optical and transmitting the SBI optical signal over a distribution fiber to a network unit located in the neighborhood of the subscribers.

摘要翻译： 在光纤传输网络中，由高速率光信号馈送的远程终端包括称为串行接口总线的内部电气链路，该串行接口总线承载24个DS0信道。 通过将SBI基带信号从电转换为光学并通过分布光纤将SBI光信号发送到位于用户附近的网络单元来扩展光传输网络。

公开(公告)号：US5508673A

公开(公告)日：1996-04-16

申请号：US72311

申请日：1993-06-02

申请人： Robert B. Staszewski

发明人： Robert B. Staszewski

IPC分类号： H01F19/04 ,  H01F27/34 ,  H01F27/28

CPC分类号： H01F19/04 ,  H01F27/34

摘要： A transformer designed for 1:N voltage transformation (where 1:N may be any rational number) at high frequencies (such as over 7 megahertz) can achieve acceptable frequency response and attendant improved values of signal attenuation and signal distortion by physically separating two or more sets of electrically tightly coupled windings and connecting one winding of different sets in parallel and the other winding of the same sets in series. This interconnection of windings to achieve a 1:N transformation ratio reduces the negative effects of the interwinding capacitance thereby providing the improved frequency response.

摘要翻译： 设计用于高频（例如超过7兆赫）的1：N电压变换（其中1：N可以是任何有理数）的变压器可以实现可接受的频率响应和随之而来的改善的信号衰减值和信号失真，通过物理分离两个或 更多套电耦合绕组，并联不同组的一个绕组并联，而另一组绕组串联。 绕组的这种互连以实现1：N变换比减小了绕组电容的负面影响，从而提供了改进的频率响应。

公开(公告)号：US5490142A

公开(公告)日：1996-02-06

申请号：US316130

申请日：1994-09-30

申请人： Claude M. Hurlocker

发明人： Claude M. Hurlocker

IPC分类号： H04J3/08 ,  H04J3/16 ,  H04Q11/04 ,  H04J3/00

CPC分类号： H04J3/08 ,  H04J3/1611 ,  H04J2203/0089

摘要： A VT group optical extension format (FIGS. 7 and 8) defines a transport frame for the transfer of 135 bytes, each byte comprising 8 bits, the format providing a line rate of 8.640 Mbit/S. Each frame comprises a transport overhead portion and a payload portion. The transport overhead portion is comprised of 27 bytes and defines various operations, administration and maintenance functions, whereas the payload portion is comprised of 108 bytes which directly correspond to one VT group of an STS-N frame (FIG. 1). The VT group optical extension format line rate is determined as an integer multiple (i) of an STS-N network element clock where i is 6 if N is 1 and i is 18 if N is 3. An optical extension interface (172) is provided between a VTG bus (140) and an optical extension (178), the interface (172) being responsive to the provision of a multiplexed VT group payload provided on the VTG bus (140) for providing a corresponding VT group optical extension transport frame on the optical extension (178), the interface (172) being further responsive to the provision of a VT group optical extension transport frame on the optical extension (178) for providing a multiplexed VT group payload and associated path overhead to the VTG bus(140).

摘要翻译： VT组光扩展格式（图7和8）定义了传输135字节的传输帧，每个字节包括8位，格式提供8.640 Mbit / S的线路速率。 每个帧包括传输开销部分和有效载荷部分。 传输开销部分由27个字节组成，并且定义了各种操作，管理和维护功能，而有效载荷部分包括直接对应于STS-N帧（图1）的一个VT组的108个字节。 VT组光扩展格式线速率被确定为STS-N网元时钟的整数倍（i），其中如果N是1，则i是6，如果N是3，则i是18。光扩展接口（172）是 提供在VTG总线（140）和光扩展（178）之间，所述接口（172）响应于提供在VTG总线（140）上提供的多路复用的VT组有效载荷，用于提供对应的VT组光扩展传输帧 在光扩展（178）上，接口（172）还响应于在光扩展（178）上提供VT组光扩展传输帧，用于向VTG总线提供多路复用的VT组有效载荷和相关联的路径开销（ 140）。