公开(公告)号：US09465068B2

公开(公告)日：2016-10-11

申请号：US13943315

申请日：2013-07-16

申请人： Elpida Memory, Inc.

发明人： Hiroaki Ikeda

IPC分类号： G01R31/26 ,  G11C29/02 ,  G01R31/28 ,  G11C29/50

CPC分类号： G01R31/2601 ,  G01R31/2884 ,  G01R31/2889 ,  G11C29/025 ,  G11C2029/5006 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Disclosed herein is a method for testing a semiconductor device, the method includes: preparing a first semiconductor chip having a first bump electrode and a first driver circuit that drives the first bump electrode, and a second semiconductor chip having a second bump electrode and a second driver circuit that drives the second bump electrode; staking the first and second semiconductor chips so that the first bump electrode and the second bump electrode are electrically connected to each other to form a current path including the first and second bump electrodes; and driving, in a test mode, the current path to a first potential by the first driver circuit while driving the current path to a second potential different from the first potential by the second driver circuit.

摘要翻译： 本发明公开了一种半导体器件的测试方法，该方法包括：制备具有第一凸块电极的第一半导体芯片和驱动第一凸块电极的第一驱动电路，以及具有第二凸块电极和第二凸块电极的第二半导体芯片 驱动所述第二凸块电极的驱动电路; 将所述第一和第二半导体芯片放置，使得所述第一凸块电极和所述第二凸起电极彼此电连接以形成包括所述第一和第二凸块电极的电流路径; 并且在测试模式中，通过第一驱动电路将当前路径驱动到第一电位，同时通过第二驱动电路将电流路径驱动到与第一电位不同的第二电位。

公开(公告)号：US20140233335A1

公开(公告)日：2014-08-21

申请号：US14169659

申请日：2014-01-31

申请人： Elpida Memory, Inc.

发明人： Yoji NISHIO ,  Tadaaki Yoshimura ,  Koji Matsuo

IPC分类号： G11C29/04

CPC分类号： G11C5/04 ,  G11C7/1057 ,  G11C29/025 ,  G11C29/44 ,  G11C2029/0409

摘要： A plurality of memory chips each have an alert terminal that notifies the outside that the memory chip has detected a predetermined error. The plurality of memory chips are mounted on memory module 100. Memory module 100 has a first transmission line connected to an alert terminal of each of the plurality of memory chips, output terminal 101 being connected to one end of the first transmission line, and a first termination resistor being connected to another end of the first transmission line.

摘要翻译： 多个存储器芯片各自具有通知外部存储器芯片已经检测到预定错误的警报终端。 多个存储器芯片安装在存储器模块100上。存储器模块100具有连接到多个存储器芯片中的每一个的警报终端的第一传输线，输出端子101连接到第一传输线的一端，并且 第一终端电阻器连接到第一传输线的另一端。

公开(公告)号：US20140187018A1

公开(公告)日：2014-07-03

申请号：US13731452

申请日：2012-12-31

申请人： INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC.

发明人： Sandra G. Malhotra ,  Hiroyuki Ode ,  Xiangxin Rui

IPC分类号： H01L49/02

CPC分类号： H01L28/56 ,  H01L28/65 ,  H01L28/75

摘要： A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a flash layer between the dielectric layer and the first electrode layer. A method for reducing the leakage current in DRAM Metal-Insulator-Metal capacitors includes forming a capping layer between the dielectric layer and the second electrode layer. The flash layer and the capping layer can be formed using an atomic layer deposition (ALD) technique. The precursor materials used for forming the flash layer and the capping layer are selected such they include at least one metal-oxygen bond. Additionally, the precursor materials are selected to also include “bulky” ligands.

摘要翻译： 一种降低DRAM金属 - 绝缘体 - 金属电容器中的漏电流的方法包括在电介质层和第一电极层之间形成闪电层。 降低DRAM金属 - 绝缘体 - 金属电容器中漏电流的方法包括在电介质层和第二电极层之间形成覆盖层。 闪光层和覆盖层可以使用原子层沉积（ALD）技术形成。 选择用于形成闪光层和覆盖层的前体材料，使得它们包括至少一种金属 - 氧键。 此外，前体材料被选择为也包括“体积大”的配体。

公开(公告)号：US20140187016A1

公开(公告)日：2014-07-03

申请号：US13727962

申请日：2012-12-27

申请人： INTERMOLECULAR, INC. ,  ELPIDA MEMORY, INC

发明人： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Deweerd ,  Arthur Gevondyan ,  Hiroyuki Ode

IPC分类号： H01L49/02

CPC分类号： H01L29/92 ,  H01L28/65 ,  H01L28/75 ,  H01L51/0021 ,  H01L51/5206

摘要： Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

公开(公告)号：US20140169057A1

公开(公告)日：2014-06-19

申请号：US14186775

申请日：2014-02-21

申请人： Elpida Memory, Inc.

发明人： Hideyuki Yoko

IPC分类号： G11C11/408 ,  G11C5/06

CPC分类号： G11C8/12 ,  G11C5/04 ,  G11C5/06 ,  G11C11/4072 ,  G11C11/408

摘要： A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.

摘要翻译： 一种用于访问多个具有多个存储体的DRAM器件的方法，所述多个DRAM器件被互连以接收公共地址和命令信号。 该方法包括：接收具有激活命令的第一芯片选择地址和第一存储体地址以激活多个DRAM器件的第一DRAM器件中的第一存储体。 在多个DRAM器件的第一DRAM器件中，对应于第一存储体地址设置第一存储体激活标志。 接收到具有列命令的第二个银行地址。 在具有与第二存储体地址相对应的置位有效标志的多个DRAM器件的第二DRAM器件中访问第二存储体。

公开(公告)号：US20140140125A1

公开(公告)日：2014-05-22

申请号：US14084824

申请日：2013-11-20

申请人： ELPIDA MEMORY, INC.

发明人： Kenji MAE ,  Mitsuru NAKURA ,  Kazuya ISHIHARA ,  Shinobu YAMAZAKI

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C13/0028 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2213/79

摘要： A semiconductor device is provided with the variable resistance element, and a control circuit that controls a resistance state of the variable resistance element by controlling current between a first end and a second end of the variable resistance element. The control circuit causes the variable resistance element to change from a first resistance state to a second resistance state by having a first current flow from the first end to the second end of the variable resistance element. In addition, after a second current smaller than the first current is made to flow from the first end to the second end of the variable resistance element, the control circuit causes the variable resistance element to change from the second resistance state to the first resistance state by having a third current flow from the second end to the first end thereof.

摘要翻译： 半导体器件设置有可变电阻元件，以及控制电路，通过控制可变电阻元件的第一端和第二端之间的电流来控制可变电阻元件的电阻状态。 控制电路通过从可变电阻元件的第一端到第二端的第一电流流动使可变电阻元件从第一电阻状态变为第二电阻状态。 此外，在小于第一电流的第二电流从可变电阻元件的第一端流到第二端之后，控制电路使可变电阻元件从第二电阻状态变为第一电阻状态 通过从第二端到第一端具有第三电流。

公开(公告)号：US20140117969A1

公开(公告)日：2014-05-01

申请号：US14149773

申请日：2014-01-07

申请人： Elpida Memory, Inc.

发明人： Akira Ide

IPC分类号： G05F3/26

CPC分类号： G05F3/16 ,  G05F3/262

摘要： A current source includes a first MOS transistor of a first channel type including a drain connected to an output terminal, and a source directly connected to a first power supply, a second MOS transistor of the first channel type including a drain connected to a gate, the gate of the second MOS transistor being connected to the gate of the first transistor, and a source directly connected to the first power supply, a third MOS transistor of a second channel type opposite the first channel type including a drain connected to the drain of the second MOS transistor, a fourth MOS transistor of the second channel type including a drain connected to the source of the third MOS transistor, a gate connected to a first bias voltage, and a source directly connected to second power supply voltage, and a control voltage generator that detects an output voltage on the output terminal and provides a shifted version of the output voltage to the gate of the third MOS transistor.

摘要翻译： 电流源包括第一沟道类型的第一MOS晶体管，包括连接到输出端的漏极和直接连接到第一电源的源极，第一沟道类型的第二MOS晶体管，包括连接到栅极的漏极， 第二MOS晶体管的栅极连接到第一晶体管的栅极和直接连接到第一电源的源极，与第一沟道类型相反的第二沟道类型的第三MOS晶体管，包括连接到漏极的漏极 第二MOS晶体管，第二沟道型的第四MOS晶体管，包括连接到第三MOS晶体管的源极的漏极，连接到第一偏置电压的栅极和直接连接到第二电源电压的源极，以及控制 电压发生器，其检测输出端子上的输出电压，并将输出电压的偏移形式提供给第三MOS晶体管的栅极。

公开(公告)号：US08681578B2

公开(公告)日：2014-03-25

申请号：US13067985

申请日：2011-07-13

申请人： Seiji Narui

发明人： Seiji Narui

IPC分类号： G11C7/00

CPC分类号： G11C11/404 ,  G11C11/406 ,  G11C11/40611

摘要： To include a refresh control circuit that generates a refresh execution signal in response to a refresh command supplied from outside, and a refresh address counter that performs a counting operation in response to activation of the refresh execution signal. The refresh control circuit generates the refresh execution signal 2n times in response to one supply of the refresh command, where n is an integer equal to or larger than 0 and equal to or less than k. The value of n is variable based on a refresh-mode specifying signal supplied from outside in synchronization with the refresh command. With this configuration, for example, a frequency of generation of the refresh execution signal in response to one supply of the refresh command can be changed dynamically, flexible control can be performed by a controller.

摘要翻译： 包括响应于从外部提供的刷新命令产生刷新执行信号的刷新控制电路和响应于刷新执行信号的激活而执行计数操作的刷新地址计数器。 刷新控制电路响应于刷新命令的一次供应而生成刷新执行信号2n次，其中n是等于或大于0且等于或小于k的整数。 基于从刷新命令同步地从外部提供的刷新模式指定信号，n的值是可变的。 通过该结构，例如，可以动态地变更响应于刷新命令的一次供给而产生刷新执行信号的频率，由控制器进行灵活的控制。

公开(公告)号：US20140078852A1

公开(公告)日：2014-03-20

申请号：US14088254

申请日：2013-11-22

申请人： Elpida Memory, Inc.

发明人： Hiroki Fujisawa

IPC分类号： G11C8/18 ,  H03L7/00

CPC分类号： G11C8/18 ,  G11C7/109 ,  G11C11/4076 ,  G11C2207/2272 ,  H03L7/00

摘要： For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.

摘要翻译： 例如，半导体器件包括第一延迟计数器，其选择是否对内部命令信号给出奇数周期等待时间; 以及第二延迟计数器，其以两个周期的间隔给出内部命令信号的等待时间。 延迟计数器串联连接。 由于用于设置等待时间的控制信息中的比特数比可设置的等待时间的类型小，所以可以减少配线密度。

公开(公告)号：US20140050004A1

公开(公告)日：2014-02-20

申请号：US13964782

申请日：2013-08-12

申请人： Elpida Memory, Inc.

发明人： Noriaki MOCHIDA

IPC分类号： G11C29/00

CPC分类号： G11C29/76 ,  G11C5/06 ,  G11C11/4097 ,  G11C29/808

摘要： Disclosed herein is a device includes first and second memory mats. The first memory mat includes first and defective memory cells and first local bit lines coupled to a first global bit line. Each of the first local bit lines is coupled to associated ones of the first memory cells, one of the first local bit lines is further coupled to the defective memory cell. The second memory mat includes second and redundant memory cells and second local bit lines coupled to a second global bit line. Each of the second local bit lines is coupled to associated ones of the second memory cells, one of the second local bit lines is further coupled to the redundant memory cell. The device further includes a control circuit accessing the redundant memory cell when the access address information coincides with the defective address information that designates the defective memory cell.

摘要翻译： 本文公开了一种包括第一和第二存储器垫的装置。 第一存储器堆包括耦合到第一全局位线的第一缺陷存储器单元和第一本地位线。 第一局部位线中的每一个被耦合到相关联的第一存储单元，第一局部位线中的一个进一步耦合到有缺陷的存储单元。 第二存储器垫包括耦合到第二全局位线的第二和冗余存储器单元和第二本地位线。 第二本地位线中的每一个被耦合到相关联的第二存储器单元，其中一个第二局部位线进一步耦合到冗余存储单元。 该设备还包括当访问地址信息与指定有缺陷的存储器单元的缺陷地址信息一致时，访问冗余存储单元的控制电路。