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公开(公告)号：US12127385B2
公开(公告)日：2024-10-22
申请号：US17565738
申请日：2021-12-30
发明人： Fujio Masuoka , Nozomu Harada
IPC分类号： H01L21/768 , H01L29/423 , H01L29/66 , H01L29/78 , H10B10/00 , H01L21/311
CPC分类号： H10B10/12 , H01L21/76816 , H01L29/4234 , H01L29/66666 , H01L29/7827 , H01L21/31116 , H01L21/31144
摘要： In formation of an SRAM cell, a band-shaped contact hole C3 is formed that does not overlap, in plan view. N+ layers 32a, 32c, 32d, and 32f formed on and at outer peripheries of the top portions of Si pillars 6a, 6c, 6d, and 6f, that partly overlaps W layers 33b and 33e on P+ layers 32b and 32e connected to the top portions of Si pillars 6b and 6e, that is connected in both the X direction and the Y direction, and that extends in the Y direction. A power supply wiring metal layer Vdd that connects the P+ layers 32b and 32e through the contact hole C3 is formed. After formation of the power supply wiring metal layer Vdd, a word wiring metal layer WL is formed so as to be orthogonal to the power supply wiring metal layer Vdd in plan view.
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公开(公告)号：US12125520B2
公开(公告)日：2024-10-22
申请号：US18194960
申请日：2023-04-03
发明人： Masakazu Kakumu , Koji Sakui , Nozomu Harada
IPC分类号： G11C11/40 , G11C11/409 , H10B12/00
CPC分类号： G11C11/409 , H10B12/20
摘要： A p layer is a semiconductor base material. An n+ layer is disposed on one extension side. An n+ layer is disposed on the opposite side in contact with the p layer. A gate insulating layer partially covers the p layer. A first gate conductor layer contacts the insulating layer. A second gate conductor layer is electrically separated from the first gate conductor layer. Memory operation is performed by applying voltage to each of the layers. In the operation, the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area is larger than the quotient of the impurity concentration of a region and the gate capacitance of a MOS structure constituted by the layers per unit area.
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公开(公告)号：US20240334675A1
公开(公告)日：2024-10-03
申请号：US18616472
申请日：2024-03-26
发明人： Koji SAKUI , Yoshihisa Iwata , Masakazu Kakumu , Nozomu Harada
IPC分类号： H10B12/00 , G11C11/404 , G11C11/4091 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4091 , G11C11/4096
摘要： In a memory device, a page is composed of memory cells arranged in rows, and pages are arranged in columns in plan view on a substrate. Each memory cell has a semiconductor base, a first impurity region and a second impurity region at both ends of the semiconductor base, and at least two gate conductor layers. The first impurity region is connected to a source line, the second impurity region to a bit line, one of the two gate conductor layers to a selection gate line, and the other to a plate line. Voltages applied to these lines are controlled to perform page erasing and writing operations. A hole group formed by impact ionization is retained within the semiconductor base to have three-valued logic storage data. A sense amplifier circuit performs determination in an order of logic storage data with a large number of holes in the hole group.
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公开(公告)号：US12096611B2
公开(公告)日：2024-09-17
申请号：US17718573
申请日：2022-04-12
发明人： Koji Sakui , Nozomu Harada
IPC分类号： H01L21/02 , G11C11/4097 , H10B12/00
CPC分类号： H10B12/20 , G11C11/4097
摘要： A memory device includes a plurality of memory cells each including a semiconductor base material that stands on a substrate in a vertical direction or that extends in a horizontal direction along the substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each of the memory cells are controlled to perform a memory write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a memory erase operation of discharging the group of positive holes from inside the channel semiconductor layer, the first impurity layer is connected to a source line, the second impurity layer is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer is connected to a first driving control line, a voltage of the word line changes from a first voltage to a second voltage that is higher than the first voltage, and a voltage of the bit lines subsequently change from a third voltage to a fourth voltage that is higher than the third voltage to perform a memory read operation of reading to the bit lines, pieces of storage data in a plurality of semiconductor base materials selected by the word line.
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公开(公告)号：US12096608B2
公开(公告)日：2024-09-17
申请号：US17493251
申请日：2021-10-04
发明人： Fujio Masuoka , Nozomu Harada , Yisuo Li
IPC分类号： H10B10/00 , H10K59/121
CPC分类号： H10B10/12 , H10K59/121 , G09G2300/0819 , G09G2300/0823
摘要： In a SRAM cell, a Si pillar, which is a selection SGT in upper row of Si pillars, is located on the left end in X direction. A Si pillar, which is a selection SGT in lower row of Si pillars, is located on the right end. The Si pillar of the lower row is present in a width of an area extended from a contact hole in Y direction in planar view. Then, the Si pillar of the upper row is present in a width of an area extended from a contact hole in Y direction in planar view. In each of the upper row and the lower row, a TiN layer, which is a gate electrode for a loading SGT and a driving SGT, is formed to contact at side surface of entire gate region in a vertical direction between the corresponding Si pillars.
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公开(公告)号：US20240196591A1
公开(公告)日：2024-06-13
申请号：US18537189
申请日：2023-12-12
发明人： Masakazu KAKUMU , Koji SAKUI , Nozomu HARADA
IPC分类号： H10B12/00 , G11C11/404 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4096
摘要： A memory device includes an n-layer 3a formed on a p-layer 1 of a substrate; an n-layer 3b extending in a vertical direction with a columnar p-layer 4 placed thereon; an insulating layer 2; a gate insulating layer 5; a gate conductor layer 22; an insulating layer 6; and a MOSFET made up of a p-layer 8, a gate insulating layer 9, n+ layers 7a and 7b, and a gate conductor layer 10. The n+ layers 7a and 7b, the gate conductor layers 5 and 10, and n-layer 3a are connected to a source line, bit line, plate line, and word line, and control line, respectively. Data retention operation is performed by controlling voltages applied to the respective layers to hold positive hole groups generated in the MOSFET, and data erase operation is performed to remove positive holes accumulated in the p-layer.
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公开(公告)号：US20240194250A1
公开(公告)日：2024-06-13
申请号：US18537121
申请日：2023-12-12
发明人： Nozomu HARADA , Koji SAKUI
IPC分类号： G11C11/4096 , G11C5/06 , G11C16/14 , G11C16/26 , H10B12/00
CPC分类号： G11C11/4096 , G11C5/063 , G11C16/14 , G11C16/26 , H10B12/20
摘要： A two-stage dynamic flash memory is formed as follows. An N+ layer 20 is formed in a pillar-shaped semiconductor layer 12, which stands on an N+ layer 2a, by performing a heat treatment, thereby producing an effect of forcing a donor impurity out into the pillar-shaped semiconductor layer 12 from a silicide layer 18, which is a layer formed to surround a middle portion of the pillar-shaped semiconductor layer 12 and contains the donor impurity. Gate oxide layers 19a to 19d are formed on a side surface of the pillar-shaped semiconductor layer 12. Etching is performed with a single mask to form first to fourth gate conductor layers 21aa, 22aa, 22ba, and 21ba and a silicide layer 18a, which have the same shape as viewed in plan view. An N+ layer 23 is formed on a top portion of the pillar-shaped semiconductor layer 12.
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公开(公告)号：US20240188272A1
公开(公告)日：2024-06-06
申请号：US18438725
申请日：2024-02-12
发明人： Kenichi KANAZAWA
IPC分类号： H10B10/00
CPC分类号： H10B10/12
摘要： In a method for forming a contact hole in electrical contact with an impurity region on a substrate present between a first semiconductor pillar and a second semiconductor pillar, a gate conductor layer at a location of the contact hole is separated into two to form a first gate conductor layer surrounding the first semiconductor pillar and a second gate conductor layer surrounding the second semiconductor pillar, and an insulating layer sidewall is formed on side walls of the first gate conductor layer and the second gate conductor layer exposed in the contact hole.
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公开(公告)号：US20240127885A1
公开(公告)日：2024-04-18
申请号：US18484089
申请日：2023-10-10
发明人： Koji SAKUI , Nozomu HARADA
IPC分类号： G11C11/4096 , G11C11/408 , G11C11/4091 , G11C11/4097 , H10B12/00
CPC分类号： G11C11/4096 , G11C11/4085 , G11C11/4091 , G11C11/4097 , H10B12/20
摘要： A memory device including a semiconductor element includes two stacked memory cells including a first impurity region, first and second gate conductor layers, a second impurity region, third and fourth gate conductor layers, and a third impurity region on a P layer substrate in order from below in a vertical direction and configured to perform data write, read, and erase operation with voltage applied to each gate conductor layer. The first impurity region is connected to a first bit line. One of the first and second gate conductor layers and the other are connected to a word line and a plate line, respectively. The third and fourth gate conductor layers are each connected to the word line or plate line connected to the second or first gate conductor layer, respectively. The second and third impurity regions are connected to a source line and a second bit line, respectively.
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公开(公告)号：US20240098967A1
公开(公告)日：2024-03-21
申请号：US18469971
申请日：2023-09-19
发明人： Koji SAKUI , Nozomu HARADA
IPC分类号： H10B12/00 , G11C11/404 , G11C11/408 , G11C11/4091 , G11C11/4096
CPC分类号： H10B12/20 , G11C11/404 , G11C11/4087 , G11C11/4091 , G11C11/4096
摘要： A memory device includes pages in a column direction on a substrate and memory cells in each page in a row direction in plan view. Each memory cell includes a semiconductor base, first and second impurity regions, connected to a source line and a bit line, respectively, at both ends of the semiconductor base, and first and second gate conductor layers, one of which is connected to a word line and the other of which is connected to a plate line. Page erase, page write, and read operations are performed by controlling voltages applied to the source, bit, word, and plate lines. A first operation of outputting data of a first page to an input/output circuit via a sense amplifier circuit and a second operation of reading data of a second page of the same bank as the first page to the bit line are performed in parallel.
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