公开(公告)号：US6100129A

公开(公告)日：2000-08-08

申请号：US189353

申请日：1998-11-09

申请人： Yeur-Luen Tu ,  Chine-Gie Lou

发明人： Yeur-Luen Tu ,  Chine-Gie Lou

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8244

CPC分类号： H01L28/82 ,  H01L27/10852 ,  H01L28/87 ,  H01L28/91

摘要： A method for manufacturing a fin-trench capacitor is disclosed. The method comprises the steps of: forming a plurality of alternating oxide and nitride layers including a top oxide layer, wherein said nitride layers are sandwiched between said oxide layers; forming a storage node contact opening in said plurality of alternating oxide and nitride layers, stopping at said landing pad; removing a portion of said nitride layers along sidewalls of said contract opening; forming a polysilicon layer over said top oxide layer and conformally along said sidewalls of said contact opening; depositing a photoresist layer into said contact opening; removing a portion of said polysilicon layer on top of said top oxide layer; forming a dielectric layer over said top oxide layer and conformally on top of said polysilicon layer along said sidewalls of said contact opening; forming a top conductive layer over said dielectric layer and in said contact opening.

摘要翻译： 公开了一种用于制造鳍状沟槽电容器的方法。 该方法包括以下步骤：形成包括顶部氧化物层的多个交替的氧化物和氮化物层，其中所述氮化物层夹在所述氧化物层之间; 在所述多个交替的氧化物和氮化物层中形成存储节点接触开口，在所述着陆焊盘处停止; 沿着所述合约开口的侧壁去除所述氮化物层的一部分; 在所述顶部氧化物层上形成多晶硅层，并沿着所述接触开口的所述侧壁共形地形成多晶硅层; 将光致抗蚀剂层沉积到所述接触开口中; 在所述顶部氧化物层的顶部上去除所述多晶硅层的一部分; 在所述顶部氧化物层上形成电介质层，并沿着所述接触开口的所述侧壁保形地位于所述多晶硅层的顶部上; 在所述介​​电层上和所述接触开口中形成顶部导电层。

公开(公告)号：US06074913A

公开(公告)日：2000-06-13

申请号：US108901

申请日：1998-07-01

申请人： Chine-Gie Lou ,  Yeur-Luen Tu

发明人： Chine-Gie Lou ,  Yeur-Luen Tu

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/8242

CPC分类号： H01L28/92 ,  H01L21/28568 ,  H01L27/10852 ,  H01L28/84

摘要： A method for manufacturing a metal-insulator-metal capacitor on a substrate is disclosed. The method comprises the steps of: forming a first dielectric layer onto said substrate; patterning and etching said first dielectric layer to form a contact opening; forming a first metal layer onto said first dielectric layer and into said contact opening; forming a barrier layer onto said first metal layer; forming a second dielectric layer onto said barrier layer; forming a discrete HSG layer onto said second dielectric layer; etching said second dielectric layer by using said HSG layer as a mask; stripping said HSG layer; etching said barrier layer and said first metal layer by using a remaining portion of said second dielectric layer as a mask; stripping said remaining portion of said second dielectric layer; patterning and etching a remaining portion of said barrier layer and a remaining portion of said first metal layer; forming a third dielectric layer over said barrier layer, said first metal layer and said first dielectric layer; and forming a second metal layer over said third dielectric layer.

摘要翻译： 公开了一种在衬底上制造金属 - 绝缘体 - 金属电容器的方法。 该方法包括以下步骤：在所述衬底上形成第一电介质层; 图案化和蚀刻所述第一介电层以形成接触开口; 在所述第一介电层上形成第一金属层并进入所述接触开口; 在所述第一金属层上形成势垒层; 在所述阻挡层上形成第二电介质层; 在所述第二介电层上形成离散的HSG层; 通过使用所述HSG层作为掩模蚀刻所述第二介质层; 剥离HSG层; 通过使用所述第二介电层的剩余部分作为掩模蚀刻所述阻挡层和所述第一金属层; 剥离所述第二电介质层的剩余部分; 图案化和蚀刻所述阻挡层的剩余部分和所述第一金属层的剩余部分; 在所述阻挡层上形成第三电介质层，所述第一金属层和所述第一介电层; 以及在所述第三介电层上形成第二金属层。

公开(公告)号：US6040603A

公开(公告)日：2000-03-21

申请号：US303769

申请日：1999-04-30

申请人： Jiuun-Jer Yang

发明人： Jiuun-Jer Yang

IPC分类号： H01L27/02 ,  H01L29/10 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L27/0266 ,  H01L29/1083 ,  H01L29/7833

摘要： A transistor formed in a semiconductor substrate having improved ESD protection is disclosed. The transistor includes a first ESD implant formed underneath the source region and the drain region of the transistor. The first ESD implant has the same impurity type as the source region and the drain region. Further, a second ESD implant is formed underneath the first ESD implant, the second ESD implant having an impurity type opposite to that of said first ESD implant. The second ESD implant also is spaced apart vertically from the first ESD implant.

摘要翻译： 公开了一种形成在具有改进的ESD保护的半导体衬底中的晶体管。 晶体管包括形成在晶体管的源极区域和漏极区域下面的第一ESD注入。 第一ESD注入具有与源区和漏区相同的杂质类型。 此外，在第一ESD注入下方形成第二ESD注入，第二ESD注入具有与所述第一ESD注入相反的杂质类型。 第二ESD植入物也与第一ESD植入物垂直地间隔开。

公开(公告)号：US6015641A

公开(公告)日：2000-01-18

申请号：US111683

申请日：1998-07-08

申请人： Yueh-Lin Chou

发明人： Yueh-Lin Chou

IPC分类号： G03F1/00 ,  G03F7/20 ,  G03F9/00

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A bitline mask pattern having reduced optical proximity effect for use in manufacturing a semiconductor memory device is disclosed. The bitline mask pattern comprises: a plurality of bitlines having a plurality of contact pads that are equally spaced apart. The bitlines are arranged parallel to each other in a columnar array and such that alternate bitlines have their contact pads aligned with each other. The contact pads having a rectangular shape, but at each corner of the contact pad, rectangular corner portions removed, and at opposing sides of the contact pads, rectangular side portions are removed.

摘要翻译： 公开了一种具有降低的用于制造半导体存储器件的光学邻近效应的位线掩模图案。 位线掩模图案包括：多个位线，其具有等间隔开的多个接触焊盘。 位线以柱状阵列彼此平行布置，并且使得替代位线具有彼此对准的接触垫。 接触垫具有矩形形状，但是在接触垫的每个角部，去除了矩形角部分，并且在接触垫的相对侧，去除矩形侧部。

公开(公告)号：US20030203544A1

公开(公告)日：2003-10-30

申请号：US10414678

申请日：2003-04-15

申请人： Worldwide Semiconductor Manufacturing Corporation

发明人： Min-Hwa Chi

IPC分类号： H01L021/00

CPC分类号： H01L27/1203

摘要： A transistor structure fabricated on a thin silicon-on-insulator layer. The transistor comprises: a body formed in a silicon layer of a first dopant type; a gate structure formed atop the body; a source adjacent a first edge of the gate structure formed of the first dopant type; and a drain adjacent a second edge of the gate structure formed of the first dopant type.

摘要翻译： 制造在薄的绝缘体上硅层上的晶体管结构。 晶体管包括：形成在第一掺杂剂类型的硅层中的主体; 门体结构形成在身上; 邻近由第一掺杂剂类型形成的栅极结构的第一边缘的源极; 以及与由第一掺杂剂类型形成的栅极结构的第二边缘相邻的漏极。

公开(公告)号：US6060742A

公开(公告)日：2000-05-09

申请号：US334080

申请日：1999-06-16

申请人： Min-hwa Chi ,  Min-Chie Jung

发明人： Min-hwa Chi ,  Min-Chie Jung

IPC分类号： H01L29/788 ,  H01L29/76 ,  G11C14/00

CPC分类号： H01L29/7885

摘要： An ETOX cell that has improved injection of electrons from a forward biased deep n-well to p-well junction underneath the channel area of a triple-well ETOX cell during substrate hot electron (SHE) programming. The ETOX cell has a control gate, a floating gate, a deep n-well formed in the substrate, a buried n+ layer in the deep n-well, a p-well formed in the n-well and atop the buried n+ layer, a drain implant formed in the p-well, and a source implant formed in the p-well. The buried n+ layer enhances the parasitic bipolar action between the n+ source/drain (as collector), the p-well (as base), and the buried n+ layer (as emitter). The parasitic transistor amplifies the amount of seed electrons injected into the p-well, which in turn results in significantly faster programming of the ETOX cell.

摘要翻译： 在衬底热电子（SHE）编程期间，ETOX电池已经从三阱ETOX电池的通道区域的正向偏置的深n阱到p阱结点改进了电子注入。 ETOX单元具有控制栅极，浮置栅极，在衬底中形成的深n阱，深n阱中的掩埋n +层，在n阱中形成的p阱以及掩埋的n +层顶部， 形成在p阱中的漏极注入，以及形成在p阱中的源极注入。 掩埋的n +层增强了n +源极/漏极（作为集电极），p阱（作为基极）和掩埋的n +层（作为发射极）之间的寄生双极性作用。 寄生晶体管放大注入到p阱中的种子电子的量，这又导致ETOX细胞的编程显着更快。

公开(公告)号：US6043131A

公开(公告)日：2000-03-28

申请号：US41827

申请日：1998-03-12

申请人： Tzu-Chiang Yu

发明人： Tzu-Chiang Yu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8222 ,  H01L21/20

CPC分类号： H01L28/82 ,  H01L28/87 ,  H01L27/10852

摘要： A method of forming a flower shaped capacitor for a DRAM over a bitline is disclosed. The method comprises the steps of: forming a first polysilicon layer over said bitline; forming a TEOS layer over said first polysilicon layer, patterning and etching an opening through said TEOS layer; depositing a second polysilicon layer; etching back said second polysilicon layer and the first polysilicon layer to form sidewall spacers in said opening; using the first polysilicon layer and sidewall spacers as a mask, etching through to said bitline and thereby removing said TEOS layer; depositing a third polysilicon layer; patterning and etching the third polysilicon layer to form a bottom storage node of the capacitor; and forming a dielectric layer and a top conductive layer over the bottom storage node.

摘要翻译： 公开了一种在位线上形成用于DRAM的花形电容器的方法。 该方法包括以下步骤：在所述位线上形成第一多晶硅层; 在所述第一多晶硅层上形成TEOS层，通过所述TEOS层图案化和蚀刻开口; 沉积第二多晶硅层; 蚀刻所述第二多晶硅层和所述第一多晶硅层，以在所述开口中形成侧壁间隔物; 使用第一多晶硅层和侧壁间隔物作为掩模，蚀刻到所述位线，从而去除所述TEOS层; 沉积第三多晶硅层; 图案化和蚀刻第三多晶硅层以形成电容器的底部存储节点; 以及在所述底部存储节点上形成介电层和顶部导电层。

公开(公告)号：US6160286A

公开(公告)日：2000-12-12

申请号：US422050

申请日：1999-10-20

申请人： Min-hwa Chi

发明人： Min-hwa Chi

IPC分类号： G11C16/02 ,  H01L29/861 ,  H01L29/78 ,  H01L33/00

CPC分类号： H01L29/8616 ,  G11C16/02

摘要： A flash memory cell formed in a semiconductor substrate is disclosed. The cell includes a deep n-well formed within the substrate. Next, a p-well is formed within the deep n-well and a n+ drain region is formed within the p-well. A floating gate is formed above the p-well being separated from the substrate by a thin oxide layer. The floating gate is formed adjacent to the n+ drain region. Finally, a control gate is formed above the floating gate, the floating gate and the control gate being separated by a dielectric layer. The new cell is read by measuring the GIDL current at n+/p-well junction, which is exponentially modulated by the floating gate potential (or its net charge). The new cell is programmed by substrate hot electron injection and is erased by F-N tunneling through the overlap area of floating gate and p-well.

摘要翻译： 公开了一种形成在半导体衬底中的闪存单元。 电池包括在衬底内形成的深n阱。 接下来，在深n阱内形成p阱，在p阱内形成n +漏极区。 在通过薄氧化物层与衬底分离的p阱之上形成浮栅。 浮置栅极与n +漏极区域相邻地形成。 最后，在浮置栅极上形成控制栅极，浮置栅极和控制栅极被介电层分开。 通过测量在n + / p阱结处的GIDL电流来读取新单元，其由浮置栅极电位（或其净电荷）指数地调制。 新电池通过衬底热电子注入进行编程，并通过F-N隧穿通过浮栅和p阱的重叠区擦除。

公开(公告)号：US06096653A

公开(公告)日：2000-08-01

申请号：US206780

申请日：1998-12-07

申请人： Yeur-Luen Tu ,  Kung Linliu

发明人： Yeur-Luen Tu ,  Kung Linliu

IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L21/302

CPC分类号： H01L21/76819 ,  H01L21/76885 ,  H01L21/32139

摘要： A method for forming a metal interconnect structure over a high topography dielectric is disclosed. The method comprises the steps of: depositing a conductive layer over the high topography dielectric layer; depositing a planarized oxide layer over the conducting layer, patterning and etching the planarized oxide layer in accordance with a desired metal interconnect pattern using the conducting layer as an etching stop; using the planarized oxide layer as a hard mask, etching the conducting layer in accordance with the desired metal interconnect pattern imparted onto the planarized oxide layer; and depositing a gap-filling oxide layer over the planarized oxide layer and the high topography dielectric layer.

摘要翻译： 公开了一种在高地形电介质上形成金属互连结构的方法。 该方法包括以下步骤：在高地形电介质层上沉积导电层; 在所述导电层上沉积平坦化的氧化物层，使用所述导电层作为蚀刻停止器，根据期望的金属互连图案图案化和蚀刻所述平坦化的氧化物层; 使用平坦化氧化物层作为硬掩模，根据施加到平坦化氧化物层上的所需金属互连图案来蚀刻导电层; 以及在所述平坦化氧化物层和所述高形貌介电层上沉积间隙填充氧化物层。

公开(公告)号：US6091635A

公开(公告)日：2000-07-18

申请号：US275523

申请日：1999-03-24

申请人： Min-hwa Chi ,  Chih Ming Chen

发明人： Min-hwa Chi ,  Chih Ming Chen

IPC分类号： G11C16/04 ,  G11C16/10 ,  H01L29/788 ,  G11C16/00

CPC分类号： H01L29/7885 ,  G11C16/0416 ,  G11C16/10

摘要： A new method for injecting electrons from a forward biased deep n-well to p-well junction underneath the channel area of a triple-well ETOX cell during substrate hot electron (SHE) programming. The ETOX cell has a control gate, a floating gate, a deep n-well formed in the substrate, a p-well formed in the n-well, a drain implant formed in the p-well, and a source implant formed in the p-well. The method comprises the steps of: forward biasing the deep n-well relative to the p-well; positively biasing the control gate by a voltage sufficient to invert the channel between the source implant and the drain implant; and positively biasing the source and drain. The SHE programming has at least 100 times higher efficiency than channel hot electron (CHE). The cell threshold voltage (V.sub.T) saturates to a value in a self-convergent manner. The SHE can also be used for tightening the Vt spread by a re-programming technique after erase.

摘要翻译： 一种用于在衬底热电子（SHE）编程期间将电子从正向偏压深n阱注入到三阱ETOX电池的沟道区域下方的p阱结的新方法。 ETOX单元具有控制栅极，浮置栅极，在衬底中形成的深n阱，在n阱中形成的p阱，形成在p阱中的漏极注入，以及形成在p阱中的源极注入 p井。 该方法包括以下步骤：相对于p阱向前偏置深n阱; 使控制栅极正向偏置足以反转源极注入和漏极注入之间的沟道的电压; 并积极偏置源极和漏极。 SHE编程具有比通道热电子（CHE）高至少100倍的效率。 电池阈值电压（VT）以自会聚的方式饱和到一个值。 擦除后，SHE也可用于通过重新编程技术来紧固Vt扩展。