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公开(公告)号：US20120025360A1
公开(公告)日：2012-02-02
申请号：US12846034
申请日：2010-07-29
申请人： Yan Xun Xue , Anup Bhalla , Jun Lu
发明人： Yan Xun Xue , Anup Bhalla , Jun Lu
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L21/56 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/97 , H01L2224/29139 , H01L2224/32245 , H01L2224/371 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40248 , H01L2224/40249 , H01L2224/45014 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73215 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/83192 , H01L2224/83385 , H01L2224/8385 , H01L2224/8485 , H01L2224/92246 , H01L2224/97 , H01L2924/00014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.
摘要翻译： 半导体封装包括引线框架，还包括芯片载体和与芯片载体相邻的多个引脚。 从芯片载体的上表面开放的多个槽将芯片载体部分地分成多个芯片安装区域。 去除凹槽的底部以完全隔离每个芯片安装区域，其中移除的凹槽的底部的宽度小于凹槽的宽度。 在一个实施例中，凹槽位于芯片载体和引脚之间，其中凹槽的底部被移除以将引脚与芯片载体隔离开，其中移除的凹槽的底部的宽度小于凹槽的宽度 。
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公开(公告)号：US08722468B2
公开(公告)日：2014-05-13
申请号：US13950666
申请日：2013-07-25
发明人： Yan Xun Xue , Anup Bhalla , Jun Lu
IPC分类号： H01L21/00
CPC分类号： H01L21/56 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/97 , H01L2224/29139 , H01L2224/32245 , H01L2224/371 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40248 , H01L2224/40249 , H01L2224/45014 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73215 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/83192 , H01L2224/83385 , H01L2224/8385 , H01L2224/8485 , H01L2224/92246 , H01L2224/97 , H01L2924/00014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.
摘要翻译： 半导体封装包括引线框架，还包括芯片载体和与芯片载体相邻的多个引脚。 从芯片载体的上表面开放的多个槽将芯片载体部分地分成多个芯片安装区域。 去除凹槽的底部以完全隔离每个芯片安装区域，其中移除的凹槽的底部的宽度小于凹槽的宽度。 在一个实施例中，凹槽位于芯片载体和引脚之间，其中凹槽的底部被移除以将引脚与芯片载体隔离开，其中移除的凹槽的底部的宽度小于凹槽的宽度 。
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公开(公告)号：US20130309816A1
公开(公告)日：2013-11-21
申请号：US13950666
申请日：2013-07-25
发明人： Yan Xun Xue , Anup Bhalla , Jun Lu
IPC分类号： H01L21/56
CPC分类号： H01L21/56 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/97 , H01L2224/29139 , H01L2224/32245 , H01L2224/371 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40248 , H01L2224/40249 , H01L2224/45014 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73215 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/83192 , H01L2224/83385 , H01L2224/8385 , H01L2224/8485 , H01L2224/92246 , H01L2224/97 , H01L2924/00014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.
摘要翻译： 半导体封装包括引线框架，还包括芯片载体和与芯片载体相邻的多个引脚。 从芯片载体的上表面开放的多个槽将芯片载体部分地分成多个芯片安装区域。 去除凹槽的底部以完全隔离每个芯片安装区域，其中移除的凹槽的底部的宽度小于凹槽的宽度。 在一个实施例中，凹槽位于芯片载体和引脚之间，其中凹槽的底部被移除以将引脚与芯片载体隔离开，其中移除的凹槽的底部的宽度小于凹槽的宽度 。
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公开(公告)号：US09184117B2
公开(公告)日：2015-11-10
申请号：US13663694
申请日：2012-10-30
申请人： Yueh-Se Ho , Yan Xun Xue , Hamza Yilmaz , Jun Lu
发明人： Yueh-Se Ho , Yan Xun Xue , Hamza Yilmaz , Jun Lu
IPC分类号： H01L29/40 , H01L23/495 , H01L23/31 , H01L23/00 , H01L21/683
CPC分类号： H01L23/4952 , H01L21/6835 , H01L23/3107 , H01L23/3142 , H01L23/49562 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/81 , H01L24/83 , H01L24/84 , H01L2221/68327 , H01L2224/1134 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/136 , H01L2224/13794 , H01L2224/13839 , H01L2224/1403 , H01L2224/16245 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/37011 , H01L2224/37013 , H01L2224/371 , H01L2224/4007 , H01L2224/40095 , H01L2224/40245 , H01L2224/40248 , H01L2224/40499 , H01L2224/405 , H01L2224/73253 , H01L2224/73255 , H01L2224/81191 , H01L2224/81801 , H01L2224/8185 , H01L2224/83801 , H01L2224/83851 , H01L2224/84385 , H01L2224/84801 , H01L2224/8485 , H01L2224/92225 , H01L2224/92226 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2924/014 , H01L2924/01082 , H01L2924/07811 , H01L2924/00012
摘要： The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.
摘要翻译： 本发明涉及一种功率半导体器件及其制备方法，特别涉及使用具有两个互连板的倒装芯片技术来制备MOSFET（金属氧化物半导体场效应晶体管）的层叠双芯片封装结构。 第一芯片被翻转并附接在基座上，使得第一芯片与第三引脚重叠; 第一芯片的背金属层通过第一互连板连接到第一引脚的接合条; 第二芯片被翻转并附接在第一互连板的主板部分上，使得第二芯片与第四引脚重叠; 并且第二芯片的背金属层通过第二互连板连接到第二引脚的接合条。
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公开(公告)号：US20140117523A1
公开(公告)日：2014-05-01
申请号：US13663694
申请日：2012-10-30
申请人： Yueh-Se Ho , Yan Xun Xue , Hamza Yilmaz , Jun Lu
发明人： Yueh-Se Ho , Yan Xun Xue , Hamza Yilmaz , Jun Lu
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/4952 , H01L21/6835 , H01L23/3107 , H01L23/3142 , H01L23/49562 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/81 , H01L24/83 , H01L24/84 , H01L2221/68327 , H01L2224/1134 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/136 , H01L2224/13794 , H01L2224/13839 , H01L2224/1403 , H01L2224/16245 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/37011 , H01L2224/37013 , H01L2224/371 , H01L2224/4007 , H01L2224/40095 , H01L2224/40245 , H01L2224/40248 , H01L2224/40499 , H01L2224/405 , H01L2224/73253 , H01L2224/73255 , H01L2224/81191 , H01L2224/81801 , H01L2224/8185 , H01L2224/83801 , H01L2224/83851 , H01L2224/84385 , H01L2224/84801 , H01L2224/8485 , H01L2224/92225 , H01L2224/92226 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2924/014 , H01L2924/01082 , H01L2924/07811 , H01L2924/00012
摘要： The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.
摘要翻译： 本发明涉及一种功率半导体器件及其制备方法，特别涉及使用具有两个互连板的倒装芯片技术来制备MOSFET（金属氧化物半导体场效应晶体管）的层叠双芯片封装结构。 第一芯片被翻转并附接在基座上，使得第一芯片与第三引脚重叠; 第一芯片的背金属层通过第一互连板连接到第一引脚的接合条; 第二芯片被翻转并附接在第一互连板的主板部分上，使得第二芯片与第四引脚重叠; 并且第二芯片的背金属层通过第二互连板连接到第二引脚的接合条。
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公开(公告)号：US08519525B2
公开(公告)日：2013-08-27
申请号：US12846034
申请日：2010-07-29
申请人： Yan Xun Xue , Anup Bhalla , Jun Lu
发明人： Yan Xun Xue , Anup Bhalla , Jun Lu
IPC分类号： H01L23/495
CPC分类号： H01L21/56 , H01L23/3107 , H01L23/49524 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/37 , H01L24/40 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/97 , H01L2224/29139 , H01L2224/32245 , H01L2224/371 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40248 , H01L2224/40249 , H01L2224/45014 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73215 , H01L2224/73221 , H01L2224/73263 , H01L2224/73265 , H01L2224/83192 , H01L2224/83385 , H01L2224/8385 , H01L2224/8485 , H01L2224/92246 , H01L2224/97 , H01L2924/00014 , H01L2924/01033 , H01L2924/01047 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.
摘要翻译： 半导体封装包括引线框架，还包括芯片载体和与芯片载体相邻的多个引脚。 从芯片载体的上表面开放的多个槽将芯片载体部分地分成多个芯片安装区域。 去除凹槽的底部以完全隔离每个芯片安装区域，其中移除的凹槽的底部的宽度小于凹槽的宽度。 在一个实施例中，凹槽位于芯片载体和引脚之间，其中凹槽的底部被移除以将引脚与芯片载体隔离开，其中移除的凹槽的底部的宽度小于凹槽的宽度 。
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