公开(公告)号：US09184117B2

公开(公告)日：2015-11-10

申请号：US13663694

申请日：2012-10-30

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Hamza Yilmaz ,  Jun Lu

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Hamza Yilmaz ,  Jun Lu

IPC分类号： H01L29/40 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683

CPC分类号： H01L23/4952 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L2221/68327 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/13794 ,  H01L2224/13839 ,  H01L2224/1403 ,  H01L2224/16245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40248 ,  H01L2224/40499 ,  H01L2224/405 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92225 ,  H01L2224/92226 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/00012

摘要： The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.

摘要翻译： 本发明涉及一种功率半导体器件及其制备方法，特别涉及使用具有两个互连板的倒装芯片技术来制备MOSFET（金属氧化物半导体场效应晶体管）的层叠双芯片封装结构。 第一芯片被翻转并附接在基座上，使得第一芯片与第三引脚重叠; 第一芯片的背金属层通过第一互连板连接到第一引脚的接合条; 第二芯片被翻转并附接在第一互连板的主板部分上，使得第二芯片与第四引脚重叠; 并且第二芯片的背金属层通过第二互连板连接到第二引脚的接合条。

公开(公告)号：US06283358B1

公开(公告)日：2001-09-04

申请号：US09650304

申请日：2000-08-29

申请人： Michael Ball

发明人： Michael Ball

IPC分类号： B23K3524

CPC分类号： B23K35/0244 ,  B23K3/0623 ,  B23K2101/40 ,  H01L24/11 ,  H01L24/13 ,  H01L24/742 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11003 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/11823 ,  H01L2224/11849 ,  H01L2224/13124 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13166 ,  H01L2224/1329 ,  H01L2224/13324 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13366 ,  H01L2224/13561 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/1379 ,  H01L2224/13839 ,  H01L2224/13844 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/81024 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H05K3/3436 ,  H05K3/3478 ,  H05K2201/0215 ,  H05K2201/083 ,  H05K2201/10234 ,  H05K2203/041 ,  H05K2203/104 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method and system for forming contacts on semiconductor components, such as wafers, dice and packages, are provided. The method employs magnets to align and hold ferromagnetic balls on bonding sites of a component substrate. The system includes a holder for holding the component substrate, and magnets on the holder aligned with bonding sites on the component. The system also includes a ball placement mechanism for placing the ferromagnetic balls on the bonding sites, and a bonding mechanism, such as an oven, or a focused energy source, for bonding the ferromagnetic balls to the bonding sites. The ferromagnetic balls can be provided as a ferromagnetic core having an outer solder layer, as a solid ferromagnetic material with a conductive adhesive outer layer, or as ferromagnetic particles embedded in a bondable matrix material. An alternate embodiment system includes a focused magnetic source for dynamically aligning the ferromagnetic balls to the bonding sites.

摘要翻译： 提供了一种用于在半导体部件上形成接触的方法和系统，例如晶片，芯片和封装。 该方法采用磁体来对准和保持组件衬底的结合位置上的铁磁性球。 该系统包括用于保持组件衬底的保持器，并且保持器上的磁体与构件上的结合位置对准。 该系统还包括用于将铁磁球放置在接合位置上的球放置机构，以及用于将铁磁球结合到接合位置的接合机构，例如烘箱或聚焦能量源。 铁磁球可以作为具有外部焊料层的铁磁芯提供，作为具有导电粘合剂外层的固体铁磁材料，或者作为嵌入可结合基质材料中的铁磁性颗粒。 替代实施例系统包括用于将铁磁球动态对准到结合位置的聚焦磁源。

公开(公告)号：US09565755B2

公开(公告)日：2017-02-07

申请号：US15062477

申请日：2016-03-07

申请人： FUJITSU LIMITED

发明人： Teru Nakanishi ,  Nobuyuki Hayashi ,  Masaru Morita ,  Yasuhiro Yoneda

IPC分类号： H05K1/11 ,  H05K1/14 ,  H05K1/02 ,  H01L23/13 ,  H01L23/498 ,  H05K3/34 ,  H05K1/18 ,  H01L23/00

CPC分类号： H05K1/0296 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/1379 ,  H01L2224/13839 ,  H01L2224/13847 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10719 ,  Y02P70/613 ,  H01L2924/00

摘要： A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.

摘要翻译： 半导体器件包括：布线板，其表面上包括第一电极焊盘; 电路板，被布置成站立在所述布线板上，并且包括连接到所述第一电极焊盘的互连; 以及半导体封装，其设置成与所述布线板面对所述电路板，并且在其表面上包括第二电极焊盘，所述第二电极焊盘连接到所述互连。

公开(公告)号：US20150221611A1

公开(公告)日：2015-08-06

申请号：US14257833

申请日：2014-04-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shin-Puu Jeng ,  Wen-Chih Chiou ,  Tu-Hao Yu ,  Hung-Jung Tu ,  Yu-Liang Lin ,  Shih-Hui Wang

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC分类号： H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13811 ,  H01L2224/13816 ,  H01L2224/13839 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/80805 ,  H01L2224/81805 ,  H01L2224/83 ,  H01L2224/83192 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/151 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/161 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

摘要： Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes coupling integrated circuit dies to a substrate, and disposing a molding material around the integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies.

摘要翻译： 公开了封装半导体器件和封装半导体器件的方法。 在一些实施例中，封装半导体器件的方法包括将集成电路管芯耦合到衬底，以及将模制材料设置在集成电路管芯周围。 盖层设置在成型材料和多个集成电路管芯之上。

公开(公告)号：US20120211549A1

公开(公告)日：2012-08-23

申请号：US13367509

申请日：2012-02-07

申请人： Takatoyo YAMAKAMI ,  Takashi KUBOTA ,  Kuniko ISHIKAWA ,  Masayuki KITAJIMA

发明人： Takatoyo YAMAKAMI ,  Takashi KUBOTA ,  Kuniko ISHIKAWA ,  Masayuki KITAJIMA

IPC分类号： B23K1/20 ,  B23K35/24

CPC分类号： H01L24/13 ,  B22F1/0014 ,  B22F1/025 ,  B23K35/262 ,  B23K35/30 ,  B23K35/3006 ,  B23K35/3013 ,  B23K35/302 ,  C22C9/00 ,  C23C24/106 ,  H01L23/49811 ,  H01L23/49883 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/0568 ,  H01L2224/05686 ,  H01L2224/1131 ,  H01L2224/1132 ,  H01L2224/11502 ,  H01L2224/13017 ,  H01L2224/13144 ,  H01L2224/13599 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13709 ,  H01L2224/13711 ,  H01L2224/13713 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13813 ,  H01L2224/13839 ,  H01L2224/13844 ,  H01L2224/13847 ,  H01L2224/13899 ,  H01L2224/13913 ,  H01L2224/13939 ,  H01L2224/13944 ,  H01L2224/13947 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16507 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2224/81055 ,  H01L2224/81075 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/8121 ,  H01L2224/8123 ,  H01L2224/81509 ,  H01L2224/81511 ,  H01L2224/81513 ,  H01L2224/81639 ,  H01L2224/81644 ,  H01L2224/81647 ,  H01L2224/81699 ,  H01L2224/81711 ,  H01L2224/81713 ,  H01L2224/81739 ,  H01L2224/81744 ,  H01L2224/8181 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/15738 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/01007 ,  H01L2924/01008 ,  H01L2924/01018 ,  H01L2924/01083 ,  H01L2924/01031 ,  H01L2924/0103 ,  H01L2924/053 ,  H01L2224/13099 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

摘要： An electro-conductive bonding material includes: metal components of a high-melting-point metal particle that have a first melting point or higher; a middle-melting-point metal particle that has a second melting point which is first temperature or higher, and second temperature or lower, the second temperature is lower than the first melting point and higher than the first temperature; and a low-melting-point metal particle that has a third melting point or lower, the third melting point is lower than the first temperature.

摘要翻译： 导电接合材料包括：具有第一熔点或更高熔点的高熔点金属颗粒的金属组分; 中间熔点金属粒子，其具有第一温度以上的第二熔点，第二温度以下，第二温度低于第一熔点且高于第一温度; 和具有第三熔点或更低熔点的低熔点金属颗粒，第三熔点低于第一温度。

公开(公告)号：US11967577B2

公开(公告)日：2024-04-23

申请号：US17498843

申请日：2021-10-12

申请人： ROHM Co., LTD.

发明人： Yosui Futamura ,  Yuto Nishiyama ,  Masahiko Nakamura

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L23/31

CPC分类号： H01L24/13 ,  H01L23/4951 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L23/3107 ,  H01L24/81 ,  H01L2224/113 ,  H01L2224/11825 ,  H01L2224/13019 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13664 ,  H01L2224/1379 ,  H01L2224/13839 ,  H01L2224/1416 ,  H01L2224/16245 ,  H01L2224/8184

摘要： Disclosed herein is a semiconductor device including a conductive member that has a main surface facing in a thickness direction, a semiconductor element that has a plurality of pads facing the main surface, a plurality of electrodes that are individually formed with respect to the plurality of pads and protrude from the plurality of pads toward the main surface, and a bonding layer for electrically bonding the main surface to the plurality of electrodes. The bonding layer includes a first region having conductivity and a second region having electrical insulation. The first region includes a metal portion. At least a part of the second region includes a resin portion.

公开(公告)号：US09585246B2

公开(公告)日：2017-02-28

申请号：US15062480

申请日：2016-03-07

申请人： FUJITSU LIMITED

发明人： Teru Nakanishi ,  Nobuyuki Hayashi ,  Masaru Morita ,  Yasuhiro Yoneda

IPC分类号： H05K1/11 ,  H05K1/14 ,  H05K1/02 ,  H01L23/13 ,  H01L23/498 ,  H05K3/34 ,  H05K1/18 ,  H01L23/00

CPC分类号： H05K1/0296 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/1379 ,  H01L2224/13839 ,  H01L2224/13847 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10287 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2201/10719 ,  Y02P70/613 ,  H01L2924/00

摘要： A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.

摘要翻译： 半导体器件包括：布线板，其表面上包括第一电极焊盘; 电路板，被布置成站立在所述布线板上，并且包括连接到所述第一电极焊盘的互连; 以及半导体封装，其设置成与所述布线板面对所述电路板，并且在其表面上包括第二电极焊盘，所述第二电极焊盘连接到所述互连。

公开(公告)号：US20170012021A1

公开(公告)日：2017-01-12

申请号：US14796381

申请日：2015-07-10

申请人： Invensas Corporation

发明人： Cyprian Emeka Uzoh

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/17 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/11442 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13309 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13355 ,  H01L2224/13409 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13813 ,  H01L2224/13839 ,  H01L2224/13844 ,  H01L2224/13855 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16104 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/8184 ,  H01L2224/83815 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/013

摘要： A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, and elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements. The conductive nanoparticles can be disposed between the surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers.

摘要翻译： 制造组件的方法可以包括在第一部件的基板的第一表面处形成第一导电元件，通过暴露于化学镀浴，在导电元件的表面上形成导电纳米颗粒，并置第一导电的表面 元件，其具有在第二部件的基板的主表面处的第二导电元件的对应表面，并且至少在并置的第一和第二导电元件的界面处将温度升高到导电纳米颗粒引起冶金接头的接合温度 在并置的第一和第二导电元件之间形成。 导电纳米颗粒可以设置在第一和第二导电元件的表面之间。 导电纳米颗粒可以具有小于100纳米的长尺寸。

公开(公告)号：US20140117523A1

公开(公告)日：2014-05-01

申请号：US13663694

申请日：2012-10-30

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Hamza Yilmaz ,  Jun Lu

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Hamza Yilmaz ,  Jun Lu

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/4952 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3142 ,  H01L23/49562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/81 ,  H01L24/83 ,  H01L24/84 ,  H01L2221/68327 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/13794 ,  H01L2224/13839 ,  H01L2224/1403 ,  H01L2224/16245 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/37013 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40248 ,  H01L2224/40499 ,  H01L2224/405 ,  H01L2224/73253 ,  H01L2224/73255 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92225 ,  H01L2224/92226 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/00012

摘要： The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.

摘要翻译： 本发明涉及一种功率半导体器件及其制备方法，特别涉及使用具有两个互连板的倒装芯片技术来制备MOSFET（金属氧化物半导体场效应晶体管）的层叠双芯片封装结构。 第一芯片被翻转并附接在基座上，使得第一芯片与第三引脚重叠; 第一芯片的背金属层通过第一互连板连接到第一引脚的接合条; 第二芯片被翻转并附接在第一互连板的主板部分上，使得第二芯片与第四引脚重叠; 并且第二芯片的背金属层通过第二互连板连接到第二引脚的接合条。

公开(公告)号：US09406650B2

公开(公告)日：2016-08-02

申请号：US14257833

申请日：2014-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu Jeng ,  Wen-Chih Chiou ,  Tu-Hao Yu ,  Hung-Jung Tu ,  Yu-Liang Lin ,  Shih-Hui Wang

IPC分类号： H01L21/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/0655 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/49827 ,  H01L23/60 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/08235 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13811 ,  H01L2224/13816 ,  H01L2224/13839 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/80805 ,  H01L2224/81805 ,  H01L2224/83 ,  H01L2224/83192 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/151 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/161 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/014

摘要： Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes coupling integrated circuit dies to a substrate, and disposing a molding material around the integrated circuit dies. A cap layer is disposed over the molding material and the plurality of integrated circuit dies.

摘要翻译： 公开了封装半导体器件和封装半导体器件的方法。 在一些实施例中，封装半导体器件的方法包括将集成电路管芯耦合到衬底，以及将模制材料设置在集成电路管芯周围。 盖层设置在成型材料和多个集成电路管芯之上。