公开(公告)号：US11694960B2

公开(公告)日：2023-07-04

申请号：US17410716

申请日：2021-08-24

Applicant: Intel Corporation

Inventor： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H05K1/18 ,  H01L23/532 ,  H01L25/18 ,  H05K3/34

CPC classification number: H01L23/5381 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/53238 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H05K1/185 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/171 ,  H01L2224/1703 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/8147 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2224/81481 ,  H01L2924/00014 ,  H01L2224/81487 ,  H01L2924/04953 ,  H01L2224/81487 ,  H01L2924/04941 ,  H01L2224/81466 ,  H01L2924/01074 ,  H01L2224/81463 ,  H01L2924/01072 ,  H01L2224/81479 ,  H01L2924/00014 ,  H01L2224/8147 ,  H01L2924/00014 ,  H01L2224/81472 ,  H01L2924/00014 ,  H01L2224/81484 ,  H01L2924/00014 ,  H01L2224/81487 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2224/81487 ,  H01L2924/0481 ,  H01L2924/01029 ,  H01L2224/81487 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2224/171 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US12132002B2

公开(公告)日：2024-10-29

申请号：US18139862

申请日：2023-04-26

Applicant: Intel Corporation

Inventor： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18 ,  H05K1/18 ,  H05K3/34

CPC classification number: H01L23/5381 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H05K1/185 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/81455 ,  H01L2924/00014 ,  H01L2224/81481 ,  H01L2924/00014 ,  H01L2224/81487 ,  H01L2924/04953 ,  H01L2224/81487 ,  H01L2924/04941 ,  H01L2224/81466 ,  H01L2924/01074 ,  H01L2224/81463 ,  H01L2924/01072 ,  H01L2224/81479 ,  H01L2924/00014 ,  H01L2224/8147 ,  H01L2924/00014 ,  H01L2224/81472 ,  H01L2924/00014 ,  H01L2224/81484 ,  H01L2924/00014 ,  H01L2224/81487 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2224/81487 ,  H01L2924/0481 ,  H01L2924/01029 ,  H01L2224/81487 ,  H01L2924/0496 ,  H01L2924/01074 ,  H01L2224/171 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US20190013271A1

公开(公告)日：2019-01-10

申请号：US16129577

申请日：2018-09-12

Applicant: INTEL CORPORATION

Inventor： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/482 ,  H01L25/18 ,  H01L23/532

CPC classification number: H01L23/5381 ,  H01L23/4821 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/0496 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0481 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US09640485B2

公开(公告)日：2017-05-02

申请号：US14836906

申请日：2015-08-26

Applicant: INTEL CORPORATION

Inventor： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/482 ,  H01L25/065 ,  H05K1/18 ,  H01L23/532 ,  H01L25/18 ,  H05K3/34

CPC classification number: H01L23/5381 ,  H01L23/4821 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/01072 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0481 ,  H01L2924/0496 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US20140353827A1

公开(公告)日：2014-12-04

申请号：US13903828

申请日：2013-05-28

Applicant: Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

Inventor： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC: H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/4821 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/01072 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0481 ,  H01L2924/0496 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于集成电路组件中的桥互连的分层互连结构的技术和配置。 在一个实施例中，装置可以包括衬底和嵌入衬底中的桥。 桥可以被配置为在两个管芯之间布置电信号。 与电桥电耦合的互连结构可以包括通孔结构，其包括第一导电材料，包含布置在通孔结构上的第二导电材料的阻挡层，以及包含布置在阻挡层上的第三导电材料的可焊材料。 第一导电材料，第二导电材料和第三导电材料可以具有不同的化学组成。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20170207168A1

公开(公告)日：2017-07-20

申请号：US15478858

申请日：2017-04-04

Applicant: INTEL CORPORATION

Inventor： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/4821 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/01072 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0481 ,  H01L2924/0496 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US20150364423A1

公开(公告)日：2015-12-17

申请号：US14836906

申请日：2015-08-26

Applicant: INTEL CORPORATION

Inventor： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/532

CPC classification number: H01L23/5381 ,  H01L23/4821 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/01072 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0481 ,  H01L2924/0496 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于集成电路组件中的桥互连的分层互连结构的技术和配置。 在一个实施例中，装置可以包括衬底和嵌入衬底中的桥。 桥可以被配置为在两个管芯之间布置电信号。 与电桥电耦合的互连结构可以包括通孔结构，其包括第一导电材料，包含布置在通孔结构上的第二导电材料的阻挡层，以及包含布置在阻挡层上的第三导电材料的可焊材料。 第一导电材料，第二导电材料和第三导电材料可以具有不同的化学组成。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09147663B2

公开(公告)日：2015-09-29

申请号：US13903828

申请日：2013-05-28

Applicant: INTEL CORPORATION

Inventor： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/482 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/4821 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/01072 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0481 ,  H01L2924/0496 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于集成电路组件中的桥互连的分层互连结构的技术和配置。 在一个实施例中，装置可以包括衬底和嵌入衬底中的桥。 桥可以被配置为在两个管芯之间布置电信号。 与电桥电耦合的互连结构可以包括通孔结构，其包括第一导电材料，包含布置在通孔结构上的第二导电材料的阻挡层，以及包含布置在阻挡层上的第三导电材料的可焊材料。 第一导电材料，第二导电材料和第三导电材料可以具有不同的化学组成。 可以描述和/或要求保护其他实施例。