公开(公告)号：US20160336258A1

公开(公告)日：2016-11-17

申请号：US15221015

申请日：2016-07-27

申请人： INTEL CORPORATION

发明人： Yueli Liu

IPC分类号： H01L23/498 ,  H05K1/18 ,  H01L23/00

CPC分类号： H01L23/49811 ,  H01L21/311 ,  H01L21/4803 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11849 ,  H01L2224/32225 ,  H01L2224/73267 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/0305 ,  H05K2201/10674 ,  H05K2203/1469

摘要： Embodiments of the present disclosure describe techniques and configurations for package assembly including an embedded element and a molded insulator material. In some embodiments, an apparatus includes an electrical element (such as a die or a bridge interconnect structure) positioned on a surface of an insulator layer, a conductive pad positioned on the surface of the insulator layer and spaced apart from the electrical element, and a molded insulator material disposed on the surface of the insulator layer adjacent to the electrical element and on the conductive pad. Other embodiments may be described and/or claimed.

公开(公告)号：US09355952B2

公开(公告)日：2016-05-31

申请号：US14798395

申请日：2015-07-13

申请人： Intel Corporation

发明人： Mark S. Hlad ,  Islam A. Salama ,  Mihir K. Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L21/44 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/50 ,  H05K1/11 ,  H05K3/10 ,  H05K3/42 ,  H01L21/56 ,  H05K3/34

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

摘要： Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

公开(公告)号：US09093313B2

公开(公告)日：2015-07-28

申请号：US14481766

申请日：2014-09-09

申请人： Intel Corporation

发明人： Mark S. Hlad ,  Islam A. Salama ,  Mihir K. Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC分类号： H01L21/4763 ,  H01L23/00 ,  H05K1/11 ,  H05K3/10 ,  H05K3/42 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H05K3/34

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

摘要： Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

摘要翻译： 封装衬底，能够减少凸起间距和封装组件。 表面级金属特征嵌入表面级电介质层中，其表面光洁度从表面电介质的顶表面突出，用于组装而无阻焊，具有焊接连接点的IC芯片。 制造封装衬底以实现多级跟踪路由，每个跟踪路由级别能够减少最小迹线宽度和间距。

公开(公告)号：US20150008578A1

公开(公告)日：2015-01-08

申请号：US14481766

申请日：2014-09-09

申请人： Intel Corporation

发明人： Mark S. Hlad ,  Islam A. Salama ,  Mihir K. Roy ,  Tao Wu ,  Yueli Liu ,  Kyu Oh Lee

IPC分类号： H01L23/00

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/1112 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11466 ,  H01L2224/119 ,  H01L2224/13005 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/165 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01103 ,  H01L2924/01108 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15321 ,  H01L2924/2064 ,  H01L2924/37001 ,  H01L2924/3841 ,  H05K1/113 ,  H05K3/107 ,  H05K3/3436 ,  H05K3/421 ,  H01L2924/00014 ,  H01L2924/00

摘要： Package substrates enabling reduced bump pitches and package assemblies thereof. Surface-level metal features are embedded in a surface-level dielectric layer with surface finish protruding from a top surface of the surface-level dielectric for assembly, without solder resist, to an IC chip having soldered connection points. Package substrates are fabricated to enable multiple levels of trace routing with each trace routing level capable of reduced minimum trace width and spacing.

公开(公告)号：US20200043852A1

公开(公告)日：2020-02-06

申请号：US16596620

申请日：2019-10-08

申请人： INTEL CORPORATION

发明人： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/482 ,  H01L25/065 ,  H05K1/18 ,  H01L23/532 ,  H01L25/18

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US10103103B2

公开(公告)日：2018-10-16

申请号：US15478858

申请日：2017-04-04

申请人： INTEL CORPORATION

发明人： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC分类号： H01L23/538 ,  H01L23/532 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US20170207168A1

公开(公告)日：2017-07-20

申请号：US15478858

申请日：2017-04-04

申请人： INTEL CORPORATION

发明人： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC分类号： H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L23/532 ,  H01L23/00

CPC分类号： H01L23/5381 ,  H01L23/4821 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/01072 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0481 ,  H01L2924/0496 ,  H01L2924/00012 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

公开(公告)号：US09502336B2

公开(公告)日：2016-11-22

申请号：US13801822

申请日：2013-03-13

申请人： Intel Corporation

发明人： Qinglei Zhang ,  Yueli Liu

IPC分类号： H05K7/10 ,  H01L23/492 ,  H01L25/16 ,  H05K3/46 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L49/02 ,  H01L23/00

CPC分类号： H01L23/492 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L25/16 ,  H01L28/60 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K3/4682 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards coreless substrates with passive device pads, as well as methods for forming coreless substrates with passive device pads and package assemblies and systems incorporating such coreless substrates. A coreless substrate may comprise a plurality of build-up layers, such as bumpless build-up layers (BBUL). In various embodiments, electrical routing features and passive device pads may be disposed on an outer surface of the substrate. In various embodiments, the passive device pads may be coupled with a conductive element disposed on or within the build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power between the passive device pads and a die coupled to the coreless substrate.

摘要翻译： 本公开的实施例涉及具有无源器件焊盘的无芯基板，以及用于形成具有无源器件焊盘和封装组件的无芯衬底以及包含这种无芯衬底的系统的方法。 无芯衬底可以包括多个堆积层，例如无凸起积聚层（BBUL）。 在各种实施例中，电路由特征和无源器件焊盘可设置在衬底的外表面上。 在各种实施例中，无源器件焊盘可以与布置在积层层上或内部的导电元件耦合。 在各种实施例中，可以在多个堆积层中限定电路径，以在无源器件焊盘与耦合到无芯衬底之间的管芯之间布置电力。

公开(公告)号：US20150364423A1

公开(公告)日：2015-12-17

申请号：US14836906

申请日：2015-08-26

申请人： INTEL CORPORATION

发明人： Yueli Liu ,  Qinglei Zhang ,  Amanda E. Schuckman ,  Rui Zhang

IPC分类号： H01L23/538 ,  H01L25/18 ,  H01L23/532

CPC分类号： H01L23/5381 ,  H01L23/4821 ,  H01L23/53238 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/26 ,  H01L24/27 ,  H01L24/33 ,  H01L24/81 ,  H01L24/82 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2224/2746 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/81463 ,  H01L2224/81466 ,  H01L2224/8147 ,  H01L2224/81472 ,  H01L2224/81479 ,  H01L2224/81481 ,  H01L2224/81484 ,  H01L2224/81487 ,  H01L2224/81815 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/3436 ,  H05K2201/10363 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01074 ,  H01L2924/01072 ,  H01L2924/0543 ,  H01L2924/01049 ,  H01L2924/0481 ,  H01L2924/0496 ,  H01L2924/00012 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及用于集成电路组件中的桥互连的分层互连结构的技术和配置。 在一个实施例中，装置可以包括衬底和嵌入衬底中的桥。 桥可以被配置为在两个管芯之间布置电信号。 与电桥电耦合的互连结构可以包括通孔结构，其包括第一导电材料，包含布置在通孔结构上的第二导电材料的阻挡层，以及包含布置在阻挡层上的第三导电材料的可焊材料。 第一导电材料，第二导电材料和第三导电材料可以具有不同的化学组成。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20150318191A1

公开(公告)日：2015-11-05

申请号：US14799516

申请日：2015-07-14

申请人： INTEL CORPORATION

发明人： Yueli Liu

IPC分类号： H01L21/56 ,  H01L21/48 ,  H01L21/311 ,  H01L23/00

CPC分类号： H01L23/49811 ,  H01L21/311 ,  H01L21/4803 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/11849 ,  H01L2224/32225 ,  H01L2224/73267 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/0305 ,  H05K2201/10674 ,  H05K2203/1469

摘要： Embodiments of the present disclosure describe techniques and configurations for package assembly including an embedded element and a molded insulator material. In some embodiments, an apparatus includes an electrical element (such as a die or a bridge interconnect structure) positioned on a surface of an insulator layer, a conductive pad positioned on the surface of the insulator layer and spaced apart from the electrical element, and a molded insulator material disposed on the surface of the insulator layer adjacent to the electrical element and on the conductive pad. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了包括嵌入元件和模制绝缘材料的封装组件的技术和配置。 在一些实施例中，装置包括位于绝缘体层的表面上的电气元件（例如管芯或桥互连结构），位于绝缘体层的表面上并与电气元件隔开的导电焊盘，以及 绝缘体材料设置在与电气元件相邻的绝缘体表面上和导电焊盘上。 可以描述和/或要求保护其他实施例。