METHOD FOR FORMING CARBON NANOTUBES WITH POST-TREATMENT STEP
    1.
    发明申请
    METHOD FOR FORMING CARBON NANOTUBES WITH POST-TREATMENT STEP 失效
    用后处理步骤形成碳纳米管的方法

    公开(公告)号:US20040250753A1

    公开(公告)日:2004-12-16

    申请号:US10302126

    申请日:2002-11-22

    摘要: Carbon nanotubes are formed on a surface of a substrate using a plasma chemical deposition process. After the nanotubes have been grown, a post-treatment step is performed on the newly formed nanotube structures. The post-treatment removes graphite and other carbon particles from the walls of the grown nanotubes and controls the thickness of the nanotube layer. The post-treatment is performed with the plasma at the same substrate temperature. For the post-treatment, the hydrogen containing gas is used as a plasma source gas. During the transition from the nanotube growth step to the post-treatment step, the pressure in the plasma process chamber is stabilized with the aforementioned purifying gas without shutting off the plasma in the chamber. This eliminates the need to purge and evacuate the plasma process chamber.

    摘要翻译: 使用等离子体化学沉积工艺在基板的表面上形成碳纳米管。 在纳米管已经生长之后,对新形成的纳米管结构进行后处理步骤。 后处理从生长的纳米管的壁上除去石墨和其他碳颗粒,并控制纳米管层的厚度。 在相同基板温度下用等离子体进行后处理。 对于后处理,使用含氢气体作为等离子体源气体。 在从纳米管生长步骤到后处理步骤的过渡期间,等离子体处理室中的压力用上述净化气体稳定,而不关闭室中的等离子体。 这样就不需要清洗和排空等离子体处理室。

    Manufacturing method for producing silicon carbide crystal using source gases
    3.
    发明申请
    Manufacturing method for producing silicon carbide crystal using source gases 有权
    使用源气制造碳化硅晶体的制造方法

    公开(公告)号:US20040231583A1

    公开(公告)日:2004-11-25

    申请号:US10872365

    申请日:2004-06-22

    摘要: A crucible, which has first member and second cylindrical body, is disposed in a lower chamber. A pedestal is disposed inside the first member, and a seed crystal is fixed to the pedestal. A second heat insulator is provided between an inlet conduit and a crucible. A first heat insulator is provided at a halfway portion of the inlet conduit. With these heat insulators, a temperature gradient occurs in the inlet conduit at a portion thereof that is closer to the crucible. A mixture gas is introduced into the crucible. The mixture gas is heated up gradually when passing through the inlet conduit and is introduced into the crucible to form SiC single crystals in high quality.

    摘要翻译: 具有第一和第二圆柱体的坩埚设置在下腔室中。 基座设置在第一构件的内部,并且晶种固定到基座。 在入口导管和坩埚之间设置第二隔热件。 第一隔热件设置在入口导管的中间部分。 利用这些隔热绝热体,入口导管在其更接近坩埚的部分处发生温度梯度。 将混合气体引入坩埚中。 混合气体在通过入口导管时逐渐加热,并被引入坩埚中以形成高质量的SiC单晶。

    Method and apparatus for plasma processing
    4.
    发明申请

    公开(公告)号:US20040221800A1

    公开(公告)日:2004-11-11

    申请号:US10857477

    申请日:2004-06-01

    发明人: Toshihiro Yanase

    CPC分类号: H01J37/32238 H01J37/32192

    摘要: In a plasma processing apparatus according to the present invention, a gas inlet port and a discharge port are provided on a chamber for introducing and discharging gas into and from the chamber respectively. A sample to be etched is placed on an electrode part, so that a high-frequency power source applies a high-frequency bias to the sample. An electromagnet provided on the periphery of a plasma generation area generates a magnetic field while a waveguide connected to an upper potion of the chamber introduces a microwave into the plasma generation area through a microwave introduction window. Electron cyclotron resonance is excited for the gas for generating plasma. At least a surface of the microwave introduction window exposed to the plasma generation area is made of quartz, while the gas contains fluorine. The apparatus having the aforementioned structure can remove a material adhering to the surface of the microwave introduction window when the sample is etched.

    Method of manufacturing a gap-filled structure of a semiconductor device
    6.
    发明申请
    Method of manufacturing a gap-filled structure of a semiconductor device 审中-公开
    制造半导体器件的间隙填充结构的方法

    公开(公告)号:US20040211357A1

    公开(公告)日:2004-10-28

    申请号:US10422760

    申请日:2003-04-24

    摘要: This invention relates to process sequence by atomic layer chemical vapor processing that includes thin film deposition for diffusion barriers in the vias, trenches or contact plug-holes followed by gap fill with ALD/CVD process and subsequent removal of the blanket film on the top by Atomic Layer Processing/Chemical Vapor Processing. The processes can be carried out in separate chambers or may be combined into one or more chambers. The apparatus employed in these processing steps allows the practitioner to rapidly complete process sequences of barrier deposition, gap fill and top layer planarization. In case of copper metallization scheme, ALD gap fill can be employed to replace electrochemical deposition of copper. Atomic layer removal of copper and other blanket films by gas phase reactions can replace the chemical-mechanical-polishing of the blanket films. Additional advantages of such processing scheme are elimination of defects, dishing, erosion, corrosion, liquid-electrolyte, slurry and other liquid waste. Benefit of such a process scheme is entrapment of the effluents and also precise metering and control of the injected amount to affect the chemical reaction in each step of the sequence that can lead to significant savings and higher chemical utilization efficiency.

    摘要翻译: 本发明涉及通过原子层化学气相处理的工艺顺序,其包括用于通孔,沟槽或接触插塞孔中的扩散阻挡层的薄膜沉积,随后用ALD / CVD工艺进行间隙填充,随后通过顶部由 原子层处理/化学气相处理。 该方法可以在单独的室中进行,或者可以组合成一个或多个室。 在这些处理步骤中使用的装置允许从业者快速完成阻挡层沉积,间隙填充和顶层平面化的处理序列。 在铜金属化方案的情况下,可以采用ALD间隙填充来替代铜的电化学沉积。 通过气相反应原子层去除铜和其他覆盖膜可以代替橡皮布膜的化学机械抛光。 这种处理方案的另外的优点是消除缺陷,凹陷,侵蚀,腐蚀,液体电解质,浆料和其它废液。 这种处理方案的益处是捕获流出物,并且精确计量和控制注入​​量以影响序列的每个步骤中的化学反应,这可以显着节省和更高的化学品利用效率。

    Silicon annealed wafer and silicon epitaxial wafer
    10.
    发明申请
    Silicon annealed wafer and silicon epitaxial wafer 有权
    硅退火晶片和硅外延晶片

    公开(公告)号:US20040194692A1

    公开(公告)日:2004-10-07

    申请号:US10809712

    申请日:2004-03-26

    摘要: A silicon annealed wafer having a sufficient thick layer free from COP defects on the surface, and a sufficient uniform BMD density in the inside can be produced by annealing either a base material wafer having nitrogen at a concentration of less than 1null1014 atoms/cm3, COP defects having a size of 0.1 nullm or less in the highest frequency of occurrence and no COP defects having a size of 0.2 nullm or more, oxygen precipitates at a density of 1null104 counts/cm2 or more, and BMDs (oxygen precipitates), where the ratio of the maximum to the minimum of the BMD density in the radial direction of the wafer is 3 or less, or a base material wafer grown at specific average temperature gradients within specific temperature ranges and specific cooling times for a single crystal at a nitrogen concentration of less than 1null1014 atoms/cm3, employing the Czochralski method. Moreover, a silicon epitaxial wafer having very small defects and a uniform BMD distribution in the inside can be formed by growing an epitaxial layer on the surface of either the first type base material wafer or the second type base material wafer. Both the silicon annealed wafer and the silicon epitaxial wafer greatly reduce the rate of producing defective devices, thereby enabling the device productivity to be enhanced.

    摘要翻译: 具有在表面上没有COP缺陷的足够厚的厚层的硅退火晶片,并且可以通过将具有小于1×10 14原子/分钟的浓度的氮的基材晶片退火来制备内部的足够均匀的BMD密度, cm 3,COP最高发生频率为0.1μm以下的COP缺陷,没有大小为0.2μm以上的COP缺陷,氧浓度为1×10 4个/ cm 2的析出物 以上,BMD(氧析出物),其中晶片的径向BMD密度的最大值与最小值的比例为3以下,或者在特定温度范围内以特定平均温度梯度生长的基材晶片 以及在小于1×10 14原子/ cm 3的氮浓度下的单晶的比冷却时间,使用Czochralski法。 此外,可以通过在第一类型基材晶片或第二类型基材晶片的表面上生长外延层来形成具有非常小缺陷和均匀的BMD分布的硅外延晶片。 硅退火晶片和硅外延晶片都大大降低了制造缺陷器件的速率,从而能够提高器件的生产率。