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公开(公告)号:US20240361800A1
公开(公告)日:2024-10-31
申请号:US18631738
申请日:2024-04-10
发明人: Juri Giovannone , Roberto Giorgio Bardelli , Andrea Gambero , Alessio Corso , Donata Rosaria Maria Nicolosi
CPC分类号: G06F1/10 , G04F10/005 , G06F1/12 , H03K5/00 , H03K2005/00013
摘要: The present invention relates to a system and a method for generating a plurality of control signals for multi-die applications. In particular, the invention relates to the generation of synchronized control signals generated by independent dies having an own local clock and provided with a common clock. In a first step, in each die, the period of the common clock signal is measured using a TDC. In further steps, in each die, a respective phase shift is evaluated and applied between the rising edge of the common clock signal and each of the rising edges of the output control signals, using delay unit.
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公开(公告)号:US12130592B2
公开(公告)日:2024-10-29
申请号:US18152747
申请日:2023-01-10
发明人: Heng Lin
IPC分类号: G04F10/00 , H03L7/099 , H03M7/30 , H04L27/227
CPC分类号: G04F10/005 , G04F10/00 , H03L7/099 , H03M7/3084 , H04L27/2272
摘要: A time-to-digital converter apparatus and a converting method thereof are provided. An output signal of a first ring oscillator circuit is counted to generate a first digital code. An output signal of a second ring oscillator circuit is counted to generate a second digital code. A corresponding third digital code is generated according to a time point of phase coincidence between one of outputs of a plurality of first delay stages of the first ring oscillator circuit and one of outputs of a plurality of second delay stages of the second ring oscillator circuit.
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公开(公告)号:US20240340031A1
公开(公告)日:2024-10-10
申请号:US18296759
申请日:2023-04-06
申请人: NXP USA, Inc.
发明人: Sai-Wang Tam , Tian Liu , Alireza Razzaghi , Alden C. Wong , Ovidiu Carnu , Wai Lau , Sridhar Reddy Narravula , Yui Lin , Sudhir Srinivasa
CPC分类号: H04B1/0475 , G04F10/005 , H03M1/1014 , H04B2001/0408
摘要: A cancellation circuit includes a limiter connected to an output of a first transmitter power amplifier that converts in input sinewave to a digital square wave and a digital to time converter (DTC) connected to the limiter. A RF digital to RF converter is connected to the DTC that converts the digital square wave input into an analog RF output. A cancellation amplifier with an input receives an output from the RF digital to RF converter and has an output connected to an output of a second transmitter power amplifier. The cancellation amplifier produces a cancellation signal to cancel an interference signal at the output of the second transmitter power amplifier from the output of the first transmitter power amplifier. A power detector is connected to the output of the second power amplifier that produces a power value detected at the output of the second power amplifier.
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公开(公告)号:US20240305301A1
公开(公告)日:2024-09-12
申请号:US18668282
申请日:2024-05-20
IPC分类号: H03L7/08 , G01R31/317 , G04F10/00 , H03L7/00
CPC分类号: H03L7/08 , G01R31/31707 , G01R31/31711 , G04F10/005 , H03L7/00
摘要: A circuit is disclosed. The circuit includes a time-to-digital converter (TDC), and an evaluation circuit coupled to the TDC and a phase-locked loop (PLL) external to the circuit.
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公开(公告)号:US12088312B2
公开(公告)日:2024-09-10
申请号:US18029448
申请日:2021-06-07
发明人: Tianyu Xie , Shaoyi Xu , Zhiyuan Zhao , Fazhan Shi , Jiangfeng Du
摘要: A method for implementing an atomic clock based on NV-14N coupling spin system in diamond and a device are provided. The method is to lock a RF frequency using a 14N zero-field splitting and output the RF frequency as a frequency standard. The method includes: applying a pulse sequence to jointly initialize NV electron spins and 14N nuclear spins; performing a Ramsey interferometry to compare a RF frequency and a 14N zero-field splitting; entangling the NV electron spin and the nuclear spin, reading out a state of nuclear spins by collecting a fluorescence signal; calculating a frequency difference between the RF frequency and the 14N zero-field splitting according to the fluorescence signal, thereby locking the RF frequency to the 14N zero-field splitting; and outputting the RF frequency as a frequency standard.
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公开(公告)号:US20240291495A1
公开(公告)日:2024-08-29
申请号:US18114847
申请日:2023-02-27
发明人: Ping LU , Bupesh PANDITA , Minhan CHEN
CPC分类号: H03L7/107 , G04F10/005 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/1077
摘要: In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.
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公开(公告)号:US12059040B2
公开(公告)日:2024-08-13
申请号:US15438052
申请日:2017-02-21
发明人: Tony Reevell
IPC分类号: A24F40/53 , A24F40/10 , A24F40/60 , G04F10/00 , G06F1/04 , G06F1/3203 , G06F9/445 , H05B1/02
CPC分类号: A24F40/53 , G04F10/00 , G06F1/04 , G06F1/3203 , G06F9/4451 , H05B1/0244 , A24F40/10 , A24F40/60 , H05B2203/021
摘要: An electrically operated aerosol generating system may include a storage portion configured to store an aerosol forming substrate, at least one heating element configured to heat the aerosol forming substrate, a sensor configured to detect an activation of the system, a clock, and electric circuitry connected to the sensor. A usage parameter associated with operation of the system may be measured and compared, to a threshold value. A usage profile of the system may be determined based on the comparison. Such operations may be repeated at different times of day. An operating mode of the system may be selectively executed based on the determined usage profile associated with the current time of day. A monitoring procedure may be ended when the measured usage parameter exceeds a threshold value, and the duration of the monitoring procedure may be compared to a threshold duration to determine the usage profile.
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公开(公告)号:US20240264210A1
公开(公告)日:2024-08-08
申请号:US18107383
申请日:2023-02-08
申请人: Apple Inc.
发明人: Ankit Srivastava , David M. Signoff
IPC分类号: G01R21/133 , G04F10/00 , H04B17/00
CPC分类号: G01R21/133 , G04F10/005 , H04B17/00
摘要: A power detector includes a first current mirror that receives an input signal and generates a mirrored input signal, a first oscillator that reverses a first current of the mirrored input signal based on a voltage of the mirrored input signal reaching a threshold, and a first counter that generates a first count of each period generated by the first oscillator. The power detector also includes a second current mirror that receives a reference signal and generates a mirrored reference signal, a second oscillator that reverses a second current of the mirrored reference signal based on a voltage of the mirrored reference signal reaching the threshold, and a second counter that generates a second count of each period generated by the second oscillator. A processor then determine the power of the input signal based on the first count and the second count.
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公开(公告)号:US12040803B2
公开(公告)日:2024-07-16
申请号:US18001618
申请日:2020-06-17
CPC分类号: H03L7/085 , G04F10/005 , H03M1/12
摘要: A frequency determination device for determining a frequency relationship between a reference signal and a clock signal. Each constituent TDC is configured to provide a digitally represented constituent output signal in response to receiving a constituent reference signal and a constituent clock signal, and the frequency determination device is configured to successively provide respectively delayed versions of the constituent clock signal of a first constituent TDC as respective constituent clock signals to the other constituent TDC:s. The reference signal provider is configured to provide the respective constituent reference. The switching circuitry is configured to provide the reference signal as the constituent clock signal to the first constituent TDC. The determination circuitry is configured to determine a number of consecutively same-valued symbols in a concatenation of the digitally represented constituent output signals of the constituent TDC:s, and to determine the frequency relationship.
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公开(公告)号:US12035877B2
公开(公告)日:2024-07-16
申请号:US16926075
申请日:2020-07-10
申请人: Arthrex, Inc.
发明人: Bruce L. Kennedy , Larry Higgins , John Batikian , Wei Yao , Craig J. Speier
CPC分类号: A61B1/00006 , A61B1/00062 , A61B1/04 , G04F10/00 , G16H20/40 , A61B1/00011 , A61B1/313
摘要: A system for determining elapsed time for a surgical procedure conducted using an endoscope is disclosed. The system may be configured to determine elapsed time for management overseeing operating rooms to determine performance metrics of the operating room such as, but not limited to, operating room consistency and frequency of unusual procedure times to assess operating room efficiency. The system may include determining insertion of an endoscope into a patient and determining removal of the endoscope from a patient. The system may then generate an elapsed surgery time based upon the insertion time of the endoscope into the patient and the removal time of the endoscope from the patient.
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